Datasheet

...........continued
Offset 0x
n0 +
index
Name Bit Pos.
0x0E
STATUS_PIPE
7:0 ERCNT[2:0] CRC16ER TOUTER PIDER DAPIDER DTGLER
0x0F 15:8
Table 38-8. Host Pipe n Descriptor Bank 1
Offset 0x
n0 +0x10
+index
Name Bit Pos.
0x00
ADDR
7:0 ADD[7:0]
0x01 15:8 ADD[15:8]
0x02 23:16 ADD[23:16]
0x03 31:24 ADD[31:24]
0x04
PCKSIZE
7:0 BYTE_COUNT[7:0]
0x05 15:8 MULTI_PACKET_SIZE[1:0 BYTE_COUNT[13:8]
0x06 23:16 MULTI_PACKET_SIZE[9:2]
0x07 31:24 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10]
0x08 7:0
0x09 15:8
0x0A STATUS_BK 7:0 ERRORFLOW CRCERR
0x0B 15:8
0x0C 7:0
0x0D 15:8
0x0E
STATUS_PIPE
7:0 ERCNT[2:0] CRC16ER TOUTER PIDER DAPIDER DTGLER
0x0F 15:8
38.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable protection is denoted by the "Enable-Protected" property in each individual register description.
Refer to the 38.5.8 Register Access Protection, PAC - Peripheral Access Controller and GCLK
Synchronization for details.
Related Links
27. PAC - Peripheral Access Controller
38.8.1 Communication Device Host Registers
SAM D5x/E5x Family Data Sheet
USB – Universal Serial Bus
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1136