Datasheet

12.10 Device Identification
Device identification relies on the ARM CoreSight component identification scheme, which allows the chip
to be identified as a SAM device implementing a DSU. The DSU contains identification registers to
differentiate the device.
12.10.1 CoreSight Identification
A system-level ARM
®
CoreSight
™
ROM table is present in the device to identify the vendor and the chip
identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug
Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0
to PID7 CoreSight ROM Table registers:
Figure 12-5. Conceptual 64-bit Peripheral ID
Table 12-2. Conceptual 64-Bit Peripheral ID Bit Descriptions
Field Size Description Location
JEP-106 CC code 4 Continuation code: 0x0 PID4
JEP-106 ID code 7 Device ID: 0x1F PID1+PID2
4KB count 4 Indicates that the CoreSight component is a ROM: 0x0 PID4
RevAnd 4 Not used; read as 0 PID3
CUSMOD 4 Not used; read as 0 PID3
PARTNUM 12 Contains 0xCD0 to indicate that DSU is present PID0+PID1
REVISION 4 DSU revision (starts at 0x0 and increments by 1 at both major
and minor revisions). Identifies DSU identification method
variants. If 0x0, this indicates that device identification can be
completed by reading the Device Identification register (DID)
PID2
For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.
12.10.2 Chip Identification Method
The DSU DID register identifies the device by implementing the following information:
• Processor identification
• Product family identification
• Product series identification
• Device select
SAM D5x/E5x Family Data Sheet
DSU - Device Service Unit
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Datasheet
DS60001507E-page 110