Datasheet

37.8.8 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x1C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
INSTREND CSRISE
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
ERROR TXC DRE RXC
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 10 – INSTREND Instruction End
This bit is set when an Instruction End has been detected.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the flag.
Bit 8 – CSRISE Chip Select Rise
The bit is set when a Chip Select Rise has been detected.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the flag.
Bit 3 – ERROR Overrun Error
This bit is set when an ERROR has occurred.
An ERROR occurs when RXDATA is loaded at least twice from the serializer.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the flag.
Bit 2 – TXC Transmission Complete
0: As soon as data is written in TXDATA.
1: TXDATA and internal shifter are empty. If a transfer delay has been defined, TXC is set after the
completion of such delay.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1099