Datasheet

Bit 2 – TXC Transmission Complete Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' will clear the corresponding interrupt request.
Value Description
0
The TXC interrupt is disabled.
1
The TXC interrupt is enabled.
Bit 1 – DRE Transmit Data Register Empty Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' will clear the corresponding interrupt request.
Value Description
0
The DRE interrupt is disabled.
1
The DRE interrupt is enabled.
Bit 0 – RXC Receive Data Register Full Interrupt Disable
Writing a '0' to this bit has no effect.
Writing a '1' will clear the corresponding interrupt request.
Value Description
0
The RXC interrupt is disabled.
1
The RXC interrupt is enabled.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1096