Datasheet

37.8.3 Baud Rate
Name: BAUD
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
DLYBS[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
BAUD[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CPHA CPOL
Access
R/W R/W
Reset 0 0
Bits 23:16 – DLYBS[7:0] Delay Before SCK
This field defines the delay from CS valid to the first valid SCK transition.
When DLYBS equals zero, the CS valid to SCK transition is 1/2 the SCK clock period.
Otherwise, the following equation determines the delay:
Equation 37-1. Delay Before SCK
   =


Bits 15:8 – BAUD[7:0] Serial Clock Baud Rate
The QSPI uses a modulus counter to derive the SCK baud rate from the module clock CLK_QSPI_AHB.
The Baud rate is selected by writing a value from 0 to 255 in the BAUD field. The following equation
determines the SCK baud rate:
Equation 37-2. SCK Baud Rate
   =

 + 1
Bit 1 – CPHA Clock Phase
CPHA determines which edge of SCK causes data to change and which edge causes data to be
captured. CPHA is used with CPOL to produce the required clock/data relationship between master and
slave devices.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1091