Datasheet

37.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
Control B
Bit 31 30 29 28 27 26 25 24
DLYCS[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DLYBCT[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATALEN[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CSMODE[1:0] SMEMREG WDRBT LOOPEN MODE
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 31:24 – DLYCS[7:0] Minimum Inactive CS Delay
This bit field defines the minimum delay between the inactivation and the activation of CS. The DLYCS
time guarantees the slave minimum deselect time.
If DLYCS is 0x00, one CLK_QSPI_AHB period will be inserted by default.
Otherwise, the following equation determines the delay:
Bits 23:16 – DLYBCT[7:0] Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing
the chip select. The delay is always inserted after each transfer and before removing the chip select if
needed.
When DLYBCT=0x00, no delay between consecutive transfers is inserted and the clock keeps its duty
cycle over the character transfers. In Serial Memory mode (MODE=1), DLYBCT is ignored and no delay
is inserted. Otherwise, the following equation determines the delay:
Bits 11:8 – DATALEN[3:0] Data Length
The DATALEN field determines the number of data bits transferred. Reserved values should not be used.
Value Name Description
0x0
8BITS 8-bits transfer
0x1
9BITS 9-bits transfer
0x2
10BITS 10-bits transfer
0x3
11BITS 11-bits transfer
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1089