Datasheet

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Offset Name Bit Pos.
0x34 INSTRCTRL
7:0 INSTR[7:0]
15:8
23:16 OPTCODE[7:0]
31:24
0x38 INSTRFRAME
7:0 DATAEN OPTCODEEN ADDREN INSTREN WIDTH[2:0]
15:8 DDREN CRMODE TFRTYPE[1:0] ADDRLEN OPTCODELEN[1:0]
23:16 DUMMYLEN[4:0]
31:24
0x3C
...
0x3F
Reserved
0x40 SCRAMBCTRL
7:0 RANDOMDIS ENABLE
15:8
23:16
31:24
0x44 SCRAMBKEY
7:0 KEY[7:0]
15:8 KEY[15:8]
23:16 KEY[23:16]
31:24 KEY[31:24]
37.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
Refer to the Peripheral Access Controller for more information.
Some registers are enable-protected, meaning they can only be written when the QSPI is disabled.
Enable-protection is denoted by the Enable-Protected property in each individual register description.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1087