Datasheet

The scrambling and unscrambling are performed on-the-fly without impacting the throughput.
The scrambling method depends on the user-configurable Scrambling User Key in the Scrambling Key
register (SCRAMBKEY.KEY). This register is only accessible in write mode.
By default, the scrambling and unscrambling algorithm includes the scrambling user key, plus a device-
dependent random value. This random value is not included when the Scrambling/Unscrambling Random
Value Disable bit in the Scrambling Mode register (SCRAMBCTRL.RANDOMDIS) is written to ‘1’.
The random value is neither user configurable nor readable. If SCRAMBCTRL.RANDOMDIS=0, data
scrambled by a given circuit cannot be unscrambled by a different circuit.
If SCRAMBCTRL.RANDOMDIS=1, the scrambling/unscrambling algorithm includes only the scrambling
user key, making it possible to manage data by different circuits. Note that the same key must be used by
the different circuits.
The scrambling user key must be securely stored in a reliable non-volatile memory in order to recover
data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is
lost.
37.6.10 DMA Operation
The QSPI generates the following DMA requests:
• Data received (RX): The request is set when data is available in the RXDATA register, and cleared
when RXDATA is read.
• Data transmit (TX): The request is set when the transmit buffer (TXDATA) is empty, and cleared
when TXDATA is written.
Note: If DMA and RX memory modes are selected, a QSPI memory space read operation is required to
force the first triggering.
If the CPU accesses the registers which are source of DMA request set/clear condition, the DMA request
can be lost or the DMA transfer can be corrupted.
37.6.11 Interrupts
The QSPI has the following interrupt source:
• Interrupt Request (INTREQ): Indicates that at least one bit in the Interrupt Flag Status and Clear
register (INTFLAG) is set to '1'.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is
enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or
the QSPI is reset. All interrupt requests from the peripheral are ORed together on system level to
generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to
determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1085