Datasheet

Figure 37-14. Instruction Transmission Waveform 3
CS
Write INSTRFRAME
Address
A23 A22 A21 A20 A3 A2 A1 A0
INTFLAG.INSTREND
Write INSTRADDR
SCK
MOSI / DATA0
Instruction 20h
Example 37-4. Example 4
Instruction in Single-bit SPI, without address, without option, with data write in Single-bit
SPI.
Command: SET BURST (77h)
• Write 0x0000_0077 to INSTRCTRL register.
• Write 0x0000_2090 to INSTRFRAME register.
• Read INSTRFRAME register (dummy read) to synchronize system bus accesses.
• Write data to the system bus memory space (0x0400_0000–0x0500_0000). The
address of the system bus write accesses is not used.
• Write the LASTXFR bit in CTRLA register to '1'.
• Wait for INTFLAG.INSTREND to rise.
Figure 37-15. Instruction Transmission Waveform 4
CS
Data
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
INTFLAG.INSTREND
Write AHB
Set CTRLA.LASTXFER
Write INSTRFRAME
Instruction 77h
SCK
MOSI / DATA0
Example 37-5. Example 5
Instruction in Single-bit SPI, with address in Dual SPI, without option, with data write in
Dual SPI.
Command: BYTE/PAGE PROGRAM (02h)
• Write 0x0000_0002 to INSTRCTRL register.
• Write 0x0000_30B3 to INSTRFRAME register.
• Read INSTRFRAME register (dummy read) to synchronize system bus accesses.
• Write data to the QSPI system bus memory space (0x040 00000–0x0500_0000).
The address of the first system bus write access is sent in the instruction frame.
The address of the next system bus write accesses is not used.
• Write LASTXFR bit in CTRLA register to '1'.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1082