Datasheet

37.6.8.3 Read Memory Transfer
The user can access the data of the serial memory by sending an instruction with DATAEN=1 and
TFRTYP=0x1 in the Instruction Frame register (INSTRFRAME).
In this mode the QSPI is able to read data at random address into the serial flash memory, allowing the
CPU to execute code directly from it (XIP execute-in-place).
In order to fetch data, the user must first configure the instruction frame by writing the INSTRFRAME.
Then data can be read at any address in the QSPI address space mapping. The address of the system
bus read accesses match the address of the data inside the serial Flash memory.
When Fetch Mode is enabled, several instruction frames can be sent before writing the bit LASTXFR in
the CTRLA. Each time the system bus read accesses become non-sequential (addresses are not
consecutive), a new instruction frame is sent with the corresponding address.
37.6.8.4 Continuous Read Mode
The QSPI is compatible with Continuous Read Mode (CRM) which is implemented in some Serial Flash
memories.
The CRM allows to reduce the instruction overhead by excluding the instruction code from the instruction
frame. When CRM is activated in a Serial Flash memory (by a specific option code), the instruction code
is stored in the memory. For the next instruction frames, the instruction code is not required, as the
memory uses the stored one.
In the QSPI, CRM is used when reading data from the memory (INSTFRAME.TFRTYPE=0x1). The
addresses of the system bus read accesses are often non-sequential, this leads to many instruction
frames with always the same instruction code. By disabling the sending of the instruction code, the CRM
reduces the access time of the data.
To be functional, this mode must be enabled in both the QSPI and the Serial Flash memory. The CRM is
enabled in the QSPI by setting the CRM bit in the INSTRFRAME register (INSTFRAME.CRMODE=1,
INSTFRAME.TFRTYPE must be 0x1). The CRM is enabled in the Serial Flash memory by sending a
specific option code.
CAUTION
If CRM is not supported by the Serial Flash memory or disabled, the CRMODE bit must not be
set. Otherwise, data read out the Serial Flash memory is not valid.
Figure 37-11. Continuous Read Mode
CS
Data
DATA1
DATA2
DATA3
Option
to activate the
Continuous Read Mode
in the serial flash memory
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O7
O6
O5
O4
O3
O2
O1
O0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Address
Instruction code is not
required
Option
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O7
O6
O5
O4
O3
O2
O1
O0
Data
D7
D6
D5
D4
D3
D2
D1
D0
Address
DATA0
SCK
Instruction
37.6.8.5 Instruction Frame Transmission Examples
All waveforms in the following examples describe SPI transfers in SPI Clock mode 0 (BAUD.CPOL=0 and
BAUD.CPHA=0). All system bus accesses described below refer to the system bus address phase.
System bus wait cycles and system bus data phases are not shown.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1080