Datasheet

2.3. Erases the lock row, removing the NVMCTRL security bit protection.
3. Check for completion by polling STATUSA.DONE (read as '1' when completed).
4. Reset the device to let the NVMCTRL update the fuses.
12.8 Programming
Programming the Flash or RAM memories is only possible when the device is not protected by the
NVMCTRL security bit. The programming procedure is as follows:
1. At power-up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR
state until the input supply is above the POR threshold (refer to Power-on Reset (POR)
characteristics). The system continues to be held in this Static state until the internally regulated
supplies have reached a safe Operating state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and
any Bus Clocks that do not have clock gate control). Internal Resets are maintained due to the
external Reset.
3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold-
Plugging procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives
a clock.
5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system
is released.
6. A chip erase is issued to ensure that the Flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After the operation is completed, the chip can be restarted either by asserting RESET or toggling
power. Make sure that the SWCLK pin is high when releasing RESET to prevent extending the
CPU Reset.
Related Links
25. NVMCTRL – Nonvolatile Memory Controller
12.9 Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools
when the device is protected, and this is accomplished by setting the NVMCTRL security bit. This
Protected state can be removed by issuing a chip erase (refer to 12.7 Chip Erase). When the device is
protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU
commands are restricted. When issuing a chip erase, sensitive information is erased from volatile
memory and Flash.
The DSU implements a security filter that monitors the AHB transactions inside the DAP. If the device is
protected, then AHB-AP read/write accesses outside the DSU external address range are discarded,
causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface
v5 Architecture Specification on http://www.arm.com).
The DSU is intended to be accessed either:
• Internally from the CPU, without any limitation, even when the device is protected
• Externally from a debug adapter, with some restrictions when the device is protected
SAM D5x/E5x Family Data Sheet
DSU - Device Service Unit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 108