Datasheet

• OPTCODELEN field configures the option code length (0 -> 1-bit / 1 -> 2-bit / 2 -> 4-bit / 3 -> 8-bit).
The value written in OPTCODELEN must be consistent with value written in the field WIDTH. For
example: OPTCODELEN = 0 (1-bit option code) is not coherent with WIDTH = 6 (option code sent
with QuadSPI protocol, thus the minimum length of the option code is 4-bit).
• ADDRLEN bit configures the address length (0 -> 24 bits / 1-> 32 bits)
• TFRTYPE field defines which type of data transfer must be performed.
• DUMMYLEN field configures the number of dummy cycles when reading data from the serial flash
memory. Between the address/option and the data, with some instructions, dummy cycles are
inserted by the serial flash memory.
If data transfer is enabled, the user can access the serial memory by reading or writing the QSPI memory
space following these rules:
• Reading from the serial memory, but not memory data (for example reading the JEDEC-ID or the
STATUS), requires TFRTYPE to be written to 0x0.
• Reading from the serial memory, and particularly memory data, requires TFRTYPE to be written to
'1'.
• Writing to the serial memory, but not memory data (for example writing the configuration or STATUS),
requires TFRTYPE to be written to 0x2.
• Writing to the serial memory, and particularly memory data, requires TFRTYPE to be written to 0x3.
If TFRTYP has a value other than 0x1 and CTRLB.SMEMREG=0, the address sent in the instruction
frame is the address of the first system bus accesses. The addresses of the subsequent access actions
are not used by the QSPI. At each system bus access, an SPI transfer is performed with the same size.
For example, a half-word system bus access leads to a 16-bit SPI transfer, and a byte system bus access
leads to an 8-bit SPI transfer.
If CTRLB.SMEMREG=1, accesses are made via the QSPI registers and the address sent in the
instruction frame is the address defined in the INSTRADDR register. Each time the INSTRFRAME or
TXDATA registers are written, an SPI transfer is performed with a byte size. Another byte is read each
time RXDATA register is read or written each time TXDATA register is written. The SPI transfer ends by
writing the LASTXFER bit in Control A register (CTRLA.LASTXFER).
If TFRTYP=0x1, the address of the first instruction frame is the one of the first read access in the QSPI
memory space. Each time the read accesses become non-sequential (addresses are not consecutive), a
new instruction frame is sent with the last system bus access address. In this way, the system can read
data at a random location in the serial memory. The size of the SPI transfers may differ from the size of
the system bus read accesses.
When data transfer is not enabled, the end of the instruction frame is indicated when the INSTREND
interrupt flag in the INTFLAG register is set. When data transfer is enabled, the user must indicate when
data transfer is completed in the QSPI memory space by setting the bit LASTXFR in the CTRLA. The end
of the instruction frame is indicated when the INSTREND interrupt flag in the INTFLAG register is set.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1078