Datasheet

Figure 37-9. Instruction Frame
CS
Data
DATA1
DATA2
DATA3
Dummy cycles
Address Option
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O7
O6
O5
O4
O3
O2
O1
O0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DATA0
SCK
Instruction EBh
37.6.8.2 Instruction Frame Sending
To send an instruction frame, the user must first configure the address to send by writing the field ADDR
in the Instruction Address Register (INSTRADDR.ADDR). This step is required if the instruction frame
includes an address and no data. When data is present, the address of the instruction is defined by the
address of the data accesses in the QSPI memory space, and not by the INSTRADDR register.
If the instruction frame includes the instruction code and/or the option code, the user must configure the
instruction code and/or the option code to send by writing the fields INST and OPTCODE bit fields in the
Instruction Control Register (INSTRCTRL.OPTCODE, INSTRCTRL.INSTR).
Then, the user must write the Instruction Frame Register (INSTRFRAME) to configure the instruction
frame depending on which instruction must be sent. If the instruction frame does not include data, writing
in this register triggers the send of the instruction frame in the QSPI. If the instruction frame includes data,
the send of the instruction frame is triggered by the first data access in the QSPI memory space.
The instruction frame is configured by the following bits and fields of INSTRFRAME:
• WIDTH field is used to configure which data lanes are used to send the instruction code, the
address, the option code and to transfer the data. It is possible to use two unidirectional data lanes
(MISO-MOSI Single-bit SPI), two bidirectional data lanes (DATA0 - DATA1 Dual SPI) or four
bidirectional data lanes (DATA0 - DATA3).
Table 37-3. WIDTH Encoding
INSTRFRAME Instruction Address/Option Data
0 Single-bit SPI Single-bit SPI Single-bit SPI
1 Single-bit SPI Single-bit SPI Dual SPI
2 Single-bit SPI Single-bit SPI Quad SPI
3 Single-bit SPI Dual SPI Dual SPI
4 Single-bit SPI Quad SPI Quad SPI
5 Dual SPI Dual SPI Dual SPI
6 Quad SPI Quad SPI Quad SPI
7 Reserved
• INSTREN bit enables sending an instruction code.
• ADDREN bit enables sending of an address after the instruction code.
• OPTCODEEN bit enables sending of an option code after the address.
• DATAEN bit enables the transfer of data (READ or PROGRAM instruction).
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1077