Datasheet

Depending on the application software handling the flags or servicing other interrupts or other tasks, the
processor may not reload the TXDATA in time to keep the Chip Select active (low). A null Delay Between
Consecutive Transfer bit field value in the CTRLB register (CTRLB.DLYBCT) will give even less time for
the processor to reload the TXDATA. With some SPI slave peripherals, requiring the Chip Select line to
remain active (low) during a full set of transfers might lead to communication errors.
To facilitate interfacing with such devices, the Chip Select Mode bit field in the CTRLB register
(CTRLB.CSMODE) can be written to 0x1. This allows the Chip Select lines to remain in their current state
(low = active) until the end of transfer is indicated by the Last Transfer bit in the CTRLA register
(CTRLA.LASTXFER). Even if the TXDATA is not reloaded the Chip Select will remain active. To have the
Chip Select line rise at the end of the last data transfer, the LASTXFER bit in the CTRLA must be set
before writing the last data to transmit into the TXDATA.
37.6.8 QSPI Serial Memory Mode
In this mode the QSPI acts as a serial flash memory controller. The QSPI can be used to read data from
the serial flash memory allowing the CPU to execute code from it (XIP execute in place). The QSPI can
also be used to control the serial flash memory (Program, Erase, Lock, etc.) by sending specific
commands. In this mode, the QSPI is compatible with single-bit SPI, Dual SPI and Quad SPI protocols.
To activate this mode, the MODE bit in Control B register must be set to one (CTRLB.MODE = 1).
In serial memory mode, data cannot be transferred by the TXDATA and the RXDATA, but by writing or
reading the QSPI memory space (0x0400 0000 – 0x0500 0000).
37.6.8.1 Instruction Frame
In order to control serial flash memories, the QSPI is able to sent instructions by the SPI bus (ex: READ,
PROGRAM, ERASE, LOCK, etc.). Because instruction set implemented in serial flash memories is
memory vendor dependant, the QSPI includes a complete instruction registers, which makes it very
flexible and compatible with all serial flash memories.
An instruction frame includes:
• An instruction code (size: 8 bits). The instruction can be optional in some cases.
• An address (size: 24 bits or 32 bits). The address is optional but is required by instructions such as
READ, PROGRAM, ERASE, LOCK. By default the address is 24 bits long, but it can be 32 bits long
to support serial flash memories larger than 128 Mbit (16 Mbyte).
• An option code (size: 1/2/4/8 bits). The option code is optional but is useful for activate the “XIP
mode” or the “Continuous Read Mode” for READ instructions, in some serial flash memory devices.
These modes allow to improve the data read latency.
• Dummy cycles. Dummy cycles are optional but required by some READ instructions.
• Data bytes are optional. Data bytes are present for data transfer instructions such as READ or
PROGRAM.
The instruction code, the address/option and the data can be sent with Single-bit SPI, Dual SPI or Quad
SPI protocols.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1076