Datasheet

Figure 37-8. Interrupt Flags Behaviour
SCK
CS
MOSI
(from master)
DRE
RXC
MISO
(from slave)
LSBMSB 123456
LSBMSB 123456
1 2 3 4 5 6 7 8
Write in TXDATA
RXDATA Read
TXC
Shift register empty
37.6.7.4 Peripheral Deselection with DMA
When the Direct Memory Access Controller is used, the Chip Select line will remain low during the whole
transfer since the Transmit Data Register Empty flag in the Interrupt Flag Status and Clear register
(INTFLAG.DRE) is managed by the DMA itself. The reloading of the TXDATA by the DMA is done as
soon as INTFLAG.DRE flag is set. In this case, setting the Chip Select Mode bit field in the Control B
register (CTRLB.CSMODE) to 0x1 is not mandatory.
However, it may happen that when other DMA channels connected to other peripherals are in use as
well, the QSPI DMA could be delayed by another DMA transfer with a higher priority on the bus. Having
DMA buffers in slower memories like flash memory or SDRAM (compared to fast internal SRAM), may
lengthen the reload time of the TXDATA by the DMA as well. This means that TXDATA might not be
reloaded in time to keep the Chip Select line low. In this case the Chip Select line may toggle between
data transfer and according to some SPI Slave devices, and the communication might get lost. Writing
CTRLB.CSMODE=0x1 can prevent this loss.
When CTRLB.CSMODE=0x0, the CS does not rise in all cases between two transfers on the same
peripheral. During a transfer on a Chip Select, the INTFLAG.DRE flag is raised as soon as the content of
the TXDATA is transferred into the internal shifter. When this flag is detected the TXDATA can be
reloaded. if this reload occurs before the end of the current transfer and if the next transfer is performed
on the same Chip Select as the current transfer, the Chip Select is not de-asserted between the two
transfers. This may lead to difficulties for interfacing with some serial peripherals requiring the Chip Select
to be de-asserted after each transfer. To facilitate interfacing with such devices, it is recommended to
write CTRLB.CSMODE to 0x2.
37.6.7.5 Peripheral Deselection without DMA
During multiple data transfers on a Chip Select without the DMA, the TXDATA is loaded by the processor,
and the Transmit Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE)
rises as soon as the content of the RXDATA is transferred into the internal shift register. When this flag is
detected high, the TXDATA can be reloaded. If this reload-by-processor occurs before the end of the
current transfer and if the next transfer is performed on the same Chip Select as the current transfer, the
Chip Select is not de-asserted between the two transfers.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1075