Datasheet

consecutive transfers. In Serial Memory mode, this delay is not programmable and DLYBCT settings
are ignored.
• The delay before SCK is programmed by writing the Delay Before SCK bit field in the BAUD register
(BAUD.DLYBS), allowing to delay the start of SPCK after the chip select has been asserted.
These delays allow the QSPI to be adapted to the interfaced peripherals and their speed and bus release
time.
Figure 37-5. Programmable Delay
DLYCS
DLYBS
DLYBCT
DLYBCT
SCK
CS
37.6.7 QSPI SPI Mode
In this mode, the QSPI acts as a regular SPI Master.
To activate this mode, the MODE bit in Control B register must be cleared (CTRLB.MODE=0).
37.6.7.1 SPI Mode Operations
The QSPI in standard SPI mode operates on the clock generated by the internal programmable baud rate
generator. It fully controls the data transfers to and from the slave connected to the SPI bus. The QSPI
drives the chip select line to the slave (CS) and the serial clock signal (SCK).
The QSPI features a single internal shift register and two holding registers: the Transmit Data Register
(TXDATA) and the Receive Data Register (RXDATA). The holding registers maintain the data flow at a
constant rate.
After enabling the QSPI, a data transfer begins when the processor writes to the TXDATA. The written
data is immediately transferred into the internal shift register and transfer on the SPI bus starts. While the
data in the internal shift register is shifted on the MOSI line, the MISO line is sampled and shifted into the
internal shift register. Receiving data cannot occur without transmitting data.
If new data is written in TXDATA during the transfer, it stays in TXDATA until the current transfer is
completed. Then, the received data is transferred from the internal shift register to the RXDATA, the data
in TXDATA is loaded into the internal shift register, and a new transfer starts.
The transfer of data written in TXDATA in the internal shift register is indicated by the Transmit Data
Register Empty (DRE) bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE). When new data
is written in TXDATA, this bit is cleared. The DRE bit is used to trigger the Transmit DMA channel.
The end of transfer is indicated by the Transmission Complete flag (INTFLAG.TXC). If the transfer delay
for the last transfer was configured to be greater than 0 (CTRLB.DLYBCT), TXC is set after the
completion of the delay. The module clock (CLK_QSPI_AHB) can be switched off at this time.
Ongoing transfer of received data from the internal shift register into RXDATA is indicated by the Receive
Data Register Full flag (INTFLAG.RXC). When the received data is read, the RXC bit is cleared.
If the RXDATA has not been read before new data is received, the Overrun Error flag in INTFLAG register
(INTFLAG.ERROR) is set. As long as this flag is set, data is loaded in RXDATA.
The SPI Mode Block Diagram shows a flow chart describing how transfers are handled.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1072