Datasheet

Figure 37-3. QSPI Transfer Modes (BAUD.CPHA = 0, 8-bit transfer)
*
SCK Cycle (for reference) 1 2 3 4 5 6 7 8
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
CS
(to slave)
LSBMSB 123456
LSBMSB 123456
* Not defined, but normally MSB of previous character received
Figure 37-4. QSPI Transfer Modes (BAUD.CPHA = 1, 8-bit transfer)
*
SCK Cycle (for reference) 1 2 3 4 5 6 7 8
SCK
(CPOL = 0)
MOSI
(from master)
MISO
(from slave)
CS
(to slave)
* Not defined, but normally LSB of previous character received
LSBMSB 123456
LSBMSB 123456
37.6.6 Transfer Delays
The QSPI supports several consecutive transfers while the chip select is active. Three delays can be
programmed to modify the transfer waveforms:
• The delay between the inactivation and the activation of CS is programmed by writing the Minimum
Inactive CS Delay bit field in the Control B register (CTRLB.DLYCS), allowing to tune the minimum
time of CS at high level.
• The delay between consecutive transfers is programmed by writing the Delay Between Consecutive
Transfers bit field in the Control B register (CTRLB.DLYBCT), allowing to insert a delay between two
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1071