Datasheet

Table Of Contents
37.6.2 Basic Operation
37.6.2.1 Initialization
After Power-On Reset, this peripheral is enabled .
37.6.2.2 Enabling, Disabling, and Resetting
The peripheral is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE).
The peripheral is disabled by writing a '0' to CTRLA.ENABLE.
The peripheral is reset by writing a '1' to the Software Reset bit (CTRLA.SWRST).
37.6.3 Transfer Data Rate
By default, the QSPI module is enabled in single data rate mode. In this operating mode, the
CLK_QSPI2X_AHB clock is not used and can be disabled.
The dual data rate operating mode is enabled by writing a '1' to the Double Data Rate Enable bit in the
Instruction Frame register (INSTRFRAME.DDREN). This operating mode requires the
CLK_QSPI2X_AHB clock and must be enabled before writing the DDREN bit.
37.6.4 Serial Clock Baudrate
The QSPI Baud rate clock is generated by dividing the module clock (CLK_QSPI_AHB) by a value
between 1 and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of
CLK_QSPI_AHB divided by 256.
37.6.5 Serial Clock Phase and Polarity
Four combinations of polarity and phase are available for data transfers. Writing the Clock Polarity bit in
the QSPI Baud register (BAUD.CPOL) selects the polarity. The Clock Phase bit in the BAUD register
programs the clock phase (BAUD.CPHA). These two parameters determine the edges of the clock signal
on which data is driven and sampled. Each of the two parameters has two possible states, resulting in
four possible combinations
Note:  The polarity/phase combinations are incompatible. Thus, the interfaced slave must use the same
parameter values to communicate.
Table 37-2. SPI Transfer Mode
Clock Mode BAUD.CPOL BAUD.CPHA Shift SCK
Edge
Capture SCK
Edge
SCK Inactive
Level
0 0 0 Falling Rising Low
1 0 1 Rising Falling Low
2 1 0 Rising Falling High
3 1 1 Falling Rising High
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1070