Datasheet

Table Of Contents

37.5.4 DMA

The DMA request lines are connected to the DMA Controller (DMAC). Using the QSPI DMA requests

requires the DMA Controller to be configured first.

Note: DMAC write access must be 32-bit aligned. If a single byte is to be written in a 32-bit word, the

rest of the word must be filled with 'ones'.

Related Links

10.2 Nested Vector Interrupt Controller

37.5.6 Events

Not applicable.

37.5.7 Debug Operation

When the CPU is halted in debug mode the QSPI continues normal operation. If the QSPI is configured in

a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper

operation or data loss may result during debugging.

37.5.8 Register Access Protection

All registers with write-access are optionally write-protected by the peripheral access controller (PAC),

except the following registers:

• Control A (CTRLA) register

• Transmit Data (TXDATA) register

• Interrupt Flag Status and Clear (INTFLAG) register

PAC write-protection is denoted by the `'PAC Write-Protection' property in the register description.

Write-protection does not apply to accesses through an external debugger.

37.6 Functional Description

37.6.1 Principle of Operation

The QSPI is a high-speed synchronous data transfer interface. It allows high-speed communication

between the device and peripheral or serial memory devices.

The QSPI operates as a master. It initiates and controls all data transactions.

When transmitting, the TXDATA register can be loaded with the next character to be transmitted during

the current transmission.

When receiving, the data is transferred to the RXDATA register, and the receiver is ready for a new

character.

SAM D5x/E5x Family Data Sheet

QSPI - Quad Serial Peripheral Interface

Datasheet

DS60001507E-page 1069