Datasheet

Related Links
32. PORT - I/O Pin Controller
37.5.2 Power Management
The QSPI will continue to operate in any Sleep mode where the selected source clock is running. The
QSPI interrupts can be used to wake up the device from sleep modes. Refer to the Power Manager
chapter for details on the different sleep modes.
37.5.3 Clocks
The QSPI bus clock (CLK_QSPI_APB) can be enabled and disabled in the Main Clock module, and the
default state of CLK_QSPI_APB can be found in the Peripheral Clock Masking section in the MCLK
chapter.
An AHB clock (CLK_QSPI_AHB) is required to clock the QSPI. This clock can be enabled and disabled in
the Main Clock module, and the default state of CLK_QSPI_AHB can be found in the Peripheral Clock
Masking section in the MCLK chapter.
A FAST clock (CLK_QSPI2X_AHB) is required to clock the QSPI. This clock can be enabled and disabled
in the Main Clock module, and the default state of CLK_QSPI2X_AHB can be found in the Peripheral
Clock Masking section in the MCLK chapter. This clock is derived from the High-Speed Clock Domain
(HS Clock Domain, frequency f
HS
).
Figure 37-2. QSPI Clock Organization
Important: The CLK_QSPI2x_AHB must be 2 times faster to CLK_QSPI_AHB when the QSPI
is operated in DDR mode. In SDR, the CLK_QSPI2x_AHB is not used.
CLK_QSPI_APB, CLK_QSPI_AHB, and CLK_QSPI2X_AHB, respectively, are all synchronous, but can
be divided by a prescaler and may run even when the module clock is turned off.
Related Links
15. MCLK – Main Clock
15.6.2.6 Peripheral Clock Masking
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1068