Datasheet

37.3 Block Diagram
Figure 37-1. QSPI Block Diagram
DMA
Peripheral
Bridge
APB
AHB
MATRIX
CPU
Peripheral Clock
MCLK
QSPI
Interrupt Control
QSPI Interrupt
SCK
MOSI/DATA0
MISO/DATA1
DATA2
DATA3
CS
37.4 Signal Description
Table 37-1. Quad-SPI Signals
Signal Description Type
SCK Serial Clock Output
CS Chip Select Output
MOSI(DATA0) Data Output (Data Input Output 0) Output (Input/Output)
MISO(DATA1) Data Input (Data Input Output 1) Input (Input/Output)
DATA2 Data Input Output 2 Input/Output
DATA3 Data Input Output 3 Input/Output
Note: MOSI and MISO are used for single-bit SPI operation
Note: DATA0-DATA1 are used for Dual SPI operation
Note: DATA0-DATA3 are used for Quad SPI operation
Refer to the pinout table for details on the pin mapping for this peripheral. One signal can be mapped to
one of several pins.
37.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
37.5.1 I/O Lines
Using the QSPI I/O lines requires the I/O pins to be configured.
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1067