Datasheet

37. QSPI - Quad Serial Peripheral Interface
37.1 Overview
The Quad SPI Interface (QSPI) circuit is a synchronous serial data link that provides communication with
external devices in Master mode.
The QSPI can be used in “SPI mode” to interface serial peripherals, such as ADCs, DACs, LCD
controllers and sensors, or in “Serial Memory Mode” to interface serial Flash memories.
The QSPI allows the system to execute code directly from a serial Flash memory (XIP) without code
shadowing to SRAM. The serial Flash memory mapping is seen in the system as other memories (ROM,
SRAM, DRAM, embedded Flash memories, etc.,).
With the support of the quad-SPI protocol, the QSPI allows the system to use high performance serial
Flash memories which are small and inexpensive, in place of larger and more expensive parallel Flash
memories.
37.2 Features
• Master SPI Interface:
– Programmable Clock Phase and Clock Polarity
– Programmable transfer delays between consecutive transfers, between clock and data, between
deactivation and activation of chip select (CS)
• SPI Mode:
– To use serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers, and sensors
– 8-bit, 16-bit, or 32-bit programmable data length
• Serial Memory Mode:
– To use serial Flash memories operating in single-bit SPI, Dual SPI and Quad SPI
– Supports “execute in place” (XIP). The system can execute code directly from a Serial Flash
memory.
– Flexible Instruction register, to be compatible with all Serial Flash memories
– 32-bit Address mode (default is 24-bit address) to support Serial Flash memories larger than 128
Mbit
– Continuous Read mode
– Scrambling/Unscrambling “On-the-Fly”
– Double data rate support
• Connection to DMA Channel Capabilities Optimizes Data Transfers
– One channel for the receiver and one channel for the transmitter
• Register Write Protection
SAM D5x/E5x Family Data Sheet
QSPI - Quad Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1066