Datasheet

Table Of Contents

• Debugger probe detection

For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture

Specification.

12.6.2 CPU Reset Extension

“CPU Reset extension” refers to the extension of the Reset phase of the CPU core after the external

Reset is released. This ensures that the CPU is not executing code at start-up while a debugger is

connects to the system. The debugger is detected on a RESET release event when SWCLK is low. At

start-up, SWCLK is internally pulled up to avoid false detection of a debugger if the SWCLK pin is left

unconnected. When the CPU is held in the Reset extension phase, the CPU Reset Extension bit of the

Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a '1' to STATUSA.CRSTEXT.

STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to STATUSA.CRSTEXT has no effect. For

security reasons, it is not possible to release the CPU Reset extension when the device is protected by

the NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the Status A register

(STATUSA.PERR).

Figure 12-2. Typical CPU Reset Extension Set and Clear Timing Diagram

DSU CRSTEXT

Clear

SWCLK

CPU reset

extension

CPU_STATE

reset

running

RESET