Datasheet

Related Links
18. PM – Power Manager
12.5.3 Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main
Clock Controller.
Related Links
18. PM – Power Manager
15. MCLK – Main Clock
15.6.2.6 Peripheral Clock Masking
12.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
22. DMAC – Direct Memory Access Controller
12.5.5 Interrupts
Not applicable.
12.5.6 Events
Not applicable.
12.5.7 Register Access Protection
Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Debug Communication Channel 0 register (DCC0)
• Debug Communication Channel 1 register (DCC1)
Note: Optional write protection is indicated by the "PAC Write Protection" property in the register
description.
Write protection does not apply for accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
12.5.8 Analog Connections
Not applicable.
12.6 Debug Operation
12.6.1 Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the
ARM processor debug resources:
• CPU Reset extension
SAM D5x/E5x Family Data Sheet
DSU - Device Service Unit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 105