Datasheet

12.3 Block Diagram
Figure 12-1. DSU Block Diagram
DSU
SWCLK
CORESIGHT ROM
DAP SECURITY FILTER
CRC-32
MBIST
CHIP ERASE
RESET
cpu_reset_extension
CPU
DAP
SWDIO
NVMCTRL
DBG
M
HIGH-SPEED
BUS MATRIX
M
S
debugger_present
DEBUGGER PROBE
INTERFACE
AHB-AP
DMA
S
DMA request
PORT
12.4 Signal Description
The DSU uses three signals to function.
Signal Name Type Description
RESET Digital Input External Reset
SWCLK Digital Input SW clock
SWDIO Digital I/O SW bidirectional data pin
Related Links
6. I/O Multiplexing and Considerations
12.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
12.5.1 I/O Lines
The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to
stretch the CPU Reset phase. For more information, refer to 12.6.3 Debugger Probe Detection. The Hot-
Plugging feature depends on the PORT configuration. If the SWCLK pin function is changed in the port or
if the PORT_MUX is disabled, the Hot-Plugging feature is disabled until a power reset or an external
Reset is performed.
12.5.2 Power Management
The DSU will continue to operate in Idle mode.
SAM D5x/E5x Family Data Sheet
DSU - Device Service Unit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 104