Datasheet

36.8.6 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ERROR DRDY AMATCH PREC
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 – ERROR Error
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in
the STATUS register. The corresponding bits in STATUS are LENERR, SEXTTOUT, LOWTOUT, COLL,
and BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – DRDY Data Ready
This flag is set when a I
2
C slave byte transmission is successfully completed.
The flag is cleared by hardware when either:
• Writing to the DATA register.
• Reading the DATA register with Smart mode enabled.
• Writing a valid command to the CMD register.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready Interrupt flag.
Bit 1 – AMATCH Address Match
This flag is set when the I
2
C slave address match logic detects that a valid address has been received.
The flag is cleared by hardware when CTRL.CMD is written.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match Interrupt flag. When cleared, an ACK/NACK will be sent
according to CTRLB.ACKACT.
Bit 0 – PREC Stop Received
This flag is set when a Stop condition is detected for a transaction being processed. A Stop condition
detected between a bus master and another slave will not set this flag, unless the PMBus Group
Command is enabled in the Control B register (CTRLB.GCMD=1).
This flag is cleared by hardware after a command is issued on the next address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received Interrupt flag.
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1039