Datasheet

36.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
ACKACT CMD[1:0]
Access
R/W W W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
AMODE[1:0] AACKEN GCMD SMEN
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Access
Reset
Bit 18 – ACKACT Acknowledge Action
This bit defines the slave's acknowledge behavior after an address or data byte is received from the
master. The acknowledge action is executed when a command is written to the CMD bits. If smart mode
is enabled (CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read.
ACKACT shall not be updated more than once between each peripheral interrupts request.
This bit is not enable-protected.
Value Description
0
Send ACK
1
Send NACK
Bits 17:16 – CMD[1:0] Command
This bit field triggers the slave operation as the below. The CMD bits are strobe bits, and always read as
zero. The operation is dependent on the slave interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH,
in addition to STATUS.DIR.
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared
when a command is given.
This bit is not enable-protected.
Table 36-3. Command Description
CMD[1:0] DIR Action
0x0 X (No action)
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1033