Datasheet

• Read data needed for transmit (TX): The request is set when data is needed for a master read
operation. The request is cleared when DATA is written.
36.6.4.1.2 Master DMA
When using the I
2
C master with DMA, the ADDR register must be written with the desired address
(ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When
ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes
in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an
automatically generated NACK (for master reads) and a STOP.
If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be
automatically generated and the length error (STATUS.LENERR) will be raised along with the
INTFLAG.ERROR interrupt.
The I
2
C master generates the following requests:
• Read data received (RX): The request is set when master read data is received. The request is
cleared when DATA is read.
• Write data needed for transmit (TX): The request is set when data is needed for a master write
operation. The request is cleared when DATA is written.
36.6.4.2 Interrupts
The I
2
C slave has the following interrupt sources. These are asynchronous interrupts. They can wake-up
the device from any Sleep mode:
• Error (ERROR)
• Data Ready (DRDY)
• Address Match (AMATCH)
• Stop Received (PREC)
The I
2
C master has the following interrupt sources. These are asynchronous interrupts. They can wake-
up the device from any Sleep mode:
• Error (ERROR)
• Slave on Bus (SB)
• Master on Bus (MB)
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the Interrupt condition is meet. Each interrupt can be individually
enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An
interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request active until the Interrupt flag is cleared, the interrupt is disabled or the I
2
C is reset.
See the INTFLAG register for details on how to clear Interrupt flags.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally
enabled for interrupt requests. Refer to Nested Vector Interrupt Controller for details.
Related Links
10.2 Nested Vector Interrupt Controller
36.6.4.3 Events
Not applicable.
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1026