Datasheet

Table 36-1. Module Request for SERCOM I
2
C Slave
Condition Request
DMA Interrupt Event
Data needed for transmit (TX)
(Slave Transmit mode)
Yes
(request cleared
when data is
written)
NA
Data received (RX) (Slave
Receive mode)
Yes
(request cleared
when data is
read)
Data Ready (DRDY) Yes
Address Match (AMATCH) Yes
Stop received (PREC) Yes
Error (ERROR) Yes
Table 36-2. Module Request for SERCOM I
2
C Master
Condition Request
DMA Interrupt Event
Data needed for transmit (TX)
(Master Transmit mode)
Yes
(request cleared
when data is
written)
NA
Data needed for transmit (RX)
(Master Transmit mode)
Yes
(request cleared
when data is
read)
Master on Bus (MB) Yes
Stop received (SB) Yes
Error (ERROR) Yes
36.6.4.1 DMA Operation
Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1.
36.6.4.1.1 Slave DMA
When using the I
2
C slave with DMA, an address match will cause the address Interrupt flag
(INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be
performed through DMA.
The I
2
C slave generates the following requests:
• Write data received (RX): The request is set when master write data is received. The request is
cleared when DATA is read.
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1025