Datasheet

after a Master Code is received. In this case, no Length Error (STATUS.LENERR) is registered,
regardless of the LENGTH.LENEN setting.
When SCL clock stretch mode is selected (CTRLA.SCLSM=1) and the transaction is a master write, the
selected Acknowledge Action (CTRLB.ACKACT) will only be used to ACK/NACK each 4th byte. All other
bytes are ACKed. This allows the user to write CTRLB.ACKACT=1 in the final interrupt, so that the last
byte in a 32-bit word will be NACKed.
Writing to the LENGTH register while a frame is in progress will produce unpredictable results. If
LENGTH.LENEN is not set and a frame is not a multiple of 4 Bytes, the remainder will be lost.
32-bit Extension Master Operation
When using the I
2
C configured as Master, the Address register must be written with the desired address
(ADDR.ADDR), and optionally, the transaction Length and transaction Length Enable bits (ADDR.LEN
and ADDR.LENEN) can be written. When ADDR.LENEN is written to '1' along with ADDR.ADDR,
ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. Then, the ADDR.LEN
bytes are transferred, followed by an automatically generated NACK (for master reads) and a STOP.
The INTFLAG.SB or INTFLAG.MB are raised for every 4 Bytes transferred. If the transaction is a master
read and ADDR.LEN is not a multiple of 4 Bytes, the final INTFLAG.SB is set when the last byte is
received.
When SCL clock stretch mode is enabled (CTRLA.SCLSM=1) and the transaction is a master read, the
selected Acknowledge Action (CTRLB.ACKACT) will only be used to ACK/NACK each 4th Byte. All other
bytes are ACKed. This allows the user to set CTRLB.ACKACT=1 in the final interrupt, so that the last byte
in a 32-bit word will be NACKed.
If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be
automatically generated, and the length error (STATUS.LENERR) is raised along with the
INTFLAG.ERROR interrupt.
36.6.4 DMA, Interrupts and Events
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the Interrupt condition is meet. Each interrupt can be individually
enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An
interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request is active until the Interrupt flag is cleared, the interrupt is disabled or the I
2
C is reset.
See the 36.8.6 INTFLAG (Slave) or 36.10.7 INTFLAG (Master) register for details on how to clear
Interrupt flags.
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1024