Datasheet

Figure 36-14. I
2
C Pad Interface
SCL/SDA
pad
I2C
Driver
SCL_OUT/
SDA_OUT
pad
PINOUT
PINOUT
SCL_IN/
SDA_IN
SCL_OUT/
SDA_OUT
36.6.3.4 Quick Command
Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command.
When quick command is enabled, the corresponding Interrupt flag (INTFLAG.SB or INTFLAG.MB) is set
immediately after the slave acknowledges the address. At this point, the software can either issue a Stop
command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.
36.6.3.5 32-bit Extension
For better system bus utilization, 32-bit data receive and transmit can be enabled by writing to the Data
32-bit bit field in the Control C register (CTRLC.DATA32B=1). When enabled, write and read transaction
to/from the DATA register are 32 bit in size.
If frames are not multiples of 4 Bytes, the Length Counter (LENGTH.LEN) and Length Enable
(LENGTH.LENEN) must be configured before data transfer begins. LENGTH.LEN must be enabled only
when CTRLC.DATA32B is enabled.
The figure below shows the order of transmit and receive when using 32-bit mode. Bytes are transmitted
or received and stored in order from 0 to 3.
Figure 36-15. 32-bit Extension Byte Ordering
BYTE0
BYTE1
BYTE2
BYTE3
APB Write/Read
31 0
Bit Position
32-bit Extension Slave Operation
The figure below shows a transaction with 32-bit Extension enabled (CTRLC.DATA32B=1). In slave
operation, the Address Match interrupt in the Interrupt Flag Status and Clear register
(INTFLAG.AMATCH) is set after the address is received and available in the DATA register. The Data
Ready interrupt (INTFLAG.DRDY) will then be raised for every 4 Bytes transferred.
Figure 36-16. 32-bit Extension Slave Operation
S
A
Byte 0
W
ADDRESS
S
W
SLAVE ADDRESS
INTERRUPT
S
W
SLAVE DATA
INTERRUPT
A
Byte 1
A
Byte 2
A
Byte 3
The LENGTH register can be written before the frame begins, or when the AMATCH interrupt is set. If the
frame size is not LENGTH.LEN Bytes, the Length Error status bit (STATUS.LENERR) is raised. If
LENGTH.LEN is not a multiple of 4 Bytes, the final INTFLAG.DRDY interrupt is raised when the last Byte
is received for master reads. For master writes, the last data byte will be automatically NACKed. On
address recognition, the internal length counter is reset in preparation for the incoming frame.
High Speed transactions start with a Full Speed Master Code. When a Master Code is detected, no data
is received and the next expected operation is a repeated start. For this reason, the length is not counted
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1023