Datasheet

Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before the I
2
C is enabled it must be configured as outlined by the following steps:
1. Select I
2
C Master or Slave mode by writing 0x4 (Slave mode) or 0x5 (Master mode) to the
Operating Mode bits in the CTRLA register (CTRLA.MODE).
2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD).
3. In Slave mode, the minimum slave setup time for the SDA can be selected in the SDA Setup Time
bit group in the Control C register (CTRLC.SDASETUP).
4. If desired, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register
(CTRLB.SMEN).
5. If desired, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register
(CTRLA.LOWTOUT).
6. In Master mode:
6.1. Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register
(CTRLA.INACTOUT).
6.2. Write the Baud Rate register (BAUD) to generate the desired baud rate.
In Slave mode:
6.1. Configure the address match configuration by writing the Address Mode value in the
CTRLB register (CTRLB.AMODE).
6.2. Set the Address and Address Mask value in the Address register (ADDR.ADDR and
ADDR.ADDRMASK) according to the address configuration.
36.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and
disabled by writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of
this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled.
36.6.2.3 I
2
C Bus State Logic
The Bus state logic includes several logic blocks that continuously monitor the activity on the I
2
C bus
lines in all Sleep modes with running GCLK_SERCOM_x clocks. The start and stop detectors and the bit
counter are all essential in the process of determining the current Bus state. The Bus state is determined
according to Bus State Diagram. Software can get the current Bus state by reading the Master Bus State
bits in the Status register (STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown
in binary.
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1010