Datasheet

Figure 36-2. Transaction Diagram Symbols
S
Sr
A
A
R
W
P
START condition
repeated START condition
STOP condition
Master driving bus
Slave driving bus
Either Master or Slave driving bus
Acknowledge (ACK)
Not Acknowledge (NACK)
Master Read
Master Write
Bus Driver Special Bus Conditions
Data Package Direction Acknowledge
'1'
'0'
'0'
'1'
Figure 36-3. Basic I
2
C Transaction Diagram
SDA
SCL
S
ADDRESS R/W ACK DATA ACK DATA ACK/NACK
6..0 7..0 7..0
P
S ADDRESS R/W A DATA PA DATA A/A
Direction
Address Packet Data Packet #0 Data Packet #1
Transaction
36.6.2 Basic Operation
36.6.2.1 Initialization
The following registers are enable-protected, meaning they can be written only when the I
2
C interface is
disabled (CTRLA.ENABLE is ‘0’):
• Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
bits
• Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command
(CTRLB.CMD) bits
• Baud register (BAUD)
• Address register (ADDR) in slave operation.
When the I
2
C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be
discarded. If the I
2
C is being disabled, writing to these registers will be completed after the disabling.
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1009