Datasheet

PAC write protection is not available for the following registers:
• Interrupt Flag Clear and Status register (INTFLAG)
• Status register (STATUS)
• Data register (DATA)
• Address register (ADDR)
Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
36.5.9 Analog Connections
Not applicable.
36.6 Functional Description
36.6.1 Principle of Operation
The I
2
C interface uses two physical lines for communication:
• Serial Data Line (SDA) for data transfer
• Serial Clock Line (SCL) for the bus clock
A transaction starts with the I
2
C master sending the Start condition, followed by a 7-bit address and a
direction bit (read or write to/from the slave).
The addressed I
2
C slave will then Acknowledge (ACK) the address, and data packet transactions can
begin. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the
data was acknowledged or not.
If a data packet is Not Acknowledged (NACK), whether by the I
2
C slave or master, the I
2
C master takes
action by either terminating the transaction by sending the Stop condition, or by sending a repeated start
to transfer more data.
The figure below illustrates the possible transaction formats and Transaction Diagram Symbols explains
the transaction symbols. These symbols will be used in the following descriptions.
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1008