Datasheet

36. SERCOM I
2
C – Inter-Integrated Circuit
36.1 Overview
The Inter-Integrated Circuit (I
2
C) interface is one of the available modes in the Serial Communication
Interface (SERCOM).
The I
2
C interface uses the SERCOM transmitter and receiver configured as shown in Figure 36-1. Labels
in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM.
A SERCOM instance can be configured to be either an I
2
C master or an I
2
C slave. Both master and slave
have an interface containing a Shift register, a transmit buffer and a receive buffer. In addition, the I
2
C
master uses the SERCOM baud-rate generator, while the I
2
C slave uses the SERCOM address match
logic.
Related Links
33. SERCOM – Serial Communication Interface
36.2 Features
SERCOM I
2
C includes the following features:
• Master or Slave Operation
• Can be used with DMA
• Philips I
2
C Compatible
• SMBus Compatible
• PMBus
™
Compatible
• Support of 100 kHz and 400 kHz, 1 MHz and 3.4 MHz I
2
C mode
• 32-bit Data Extension for better system bus utilization
• 4-Wire Operation Supported
• Physical nterface includes:
– Slew-rate limited outputs
– Filtered inputs
• Slave Operation:
– Operation in all Sleep modes
– Wake-up on address match
– 7-bit and 10-bit Address match in hardware for:
– • Unique address and/or 7-bit general call address
• Address range
• Two unique addresses can be used with DMA
Related Links
33.2 Features
SAM D5x/E5x Family Data Sheet
SERCOM I2C – Inter-Integrated Circuit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1005