Datasheet

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Table Of Contents

SAM D5x/E5x Family Data

Sheet

32-bit ARM

Cortex

-M4F MCUs with 1 Msps 12-bit ADC,

QSPI, USB, Ethernet, and PTC

Features

Operating Conditions:

• 1.71V to 3.63V, -40°C to +125°C, DC to 100 MHz

• 1.71V to 3.63V, -40°C to +105°C, DC to 120 MHz

• 1.71V to 3.63V, -40°C to +85°C, DC to 120 MHz

Core: 120 MHz Arm Cortex-M4

• 403 CoreMark

at 120 MHz

• 4 KB combined instruction cache and data cache

• 8-Zone Memory Protection Unit (MPU)

• Thumb

-2 instruction set

• Embedded Trace Module (ETM) with instruction trace stream

• Core Sight Embedded Trace Buffer (ETB)

• Trace Port Interface Unit (TPIU)

• Floating Point Unit (FPU)

Memories

• 1 MB/512 KB/256 KB in-system self-programmable Flash with:

– Error Correction Code (ECC)

– Dual bank with Read-While-Write (RWW) support

– EEPROM hardware emulation

• 128 KB, 192 KB, 256 KB SRAM main memory

– 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option

• Up to 4 KB of Tightly Coupled Memory (TCM)

• Up to 8 KB additional SRAM

– Can be retained in backup mode

• Eight 32-bit backup registers

System

• Power-on Reset (POR) and Brown-out detection (BOD)

• Internal and external clock options

• External Interrupt Controller (EIC)

• 16 external interrupts

• One non-maskable interrupt

• Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface

Power Supply

Datasheet

DS60001507E-page 1

Summary of content (2129 pages)

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SAM D5x/E5x Family Data Sheet 32-bit ARM® Cortex®-M4F MCUs with 1 Msps 12-bit ADC, QSPI, USB, Ethernet, and PTC Features Operating Conditions: • 1.71V to 3.63V, -40°C to +125°C, DC to 100 MHz • 1.71V to 3.63V, -40°C to +105°C, DC to 120 MHz • 1.71V to 3.
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SAM D5x/E5x Family Data Sheet • • • • Idle, Standby, Hibernate, Backup, and Off sleep modes SleepWalking peripherals Battery backup support Embedded Buck/LDO regulator supporting on-the-fly selection High-Performance Peripherals • 32-channel Direct Memory Access Controller (DMAC) – Built-in CRC with memory CRC generation/monitor hardware support • Up to two SD/MMC Host Controller (SDHC) – Up to 50 MHz operation – 4-bit or 1-bit interface – Compatibility with SD and SDHC memory card specification version 3
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SAM D5x/E5x Family Data Sheet • • • • • • • • • • • • • • • • – 32-bit TC with two compare/capture channels, by pairing two TCs Two 24-bit Timer/Counters for Control (TCC), with extended functions: – Up to six compare channels with optional complementary output – Generation of synchronized pulse width modulation (PWM) pattern across port pins – Deterministic fault protection, fast decay and configurable dead-time between complementary output – Dithering that increase resolution with up to 5 bit and redu
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SAM D5x/E5x Family Data Sheet • 32.768 kHz crystal oscillator (XOSC32K) – Clock failure detection • Up to two 8 MHz to 48 MHz crystal oscillator (XOSC) – Clock failure detection • 32.768 kHz ultra low-power internal oscillator (OSCULP32K) • 48 MHz Digital Frequency Locked Loop (DFLL48M) • Two 96-200 MHz Fractional Digital Phased Locked Loop (FDPLL200M) I/O • Up to 99 programmable I/O pins Qualification • AEC-Q100 Grade 1 (-40°C to 125°C) Packages Table 1.
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SAM D5x/E5x Family Data Sheet Table of Contents Features.......................................................................................................................... 1 1. Configuration Summary...........................................................................................17 2. Ordering Information................................................................................................19 3. Block Diagram...........................................................................
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SAM D5x/E5x Family Data Sheet 11.2. 11.3. 11.4. 11.5. 11.6. 11.7. 11.8. 11.9. 11.10. Features..................................................................................................................................... 81 Block Diagram............................................................................................................................ 82 Signal Description......................................................................................................................
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SAM D5x/E5x Family Data Sheet 15.4. 15.5. 15.6. 15.7. 15.8. Signal Description.................................................................................................................... 170 Product Dependencies............................................................................................................. 170 Functional Description..............................................................................................................172 Register Summary..........................
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SAM D5x/E5x Family Data Sheet 20.2. 20.3. 20.4. 20.5. 20.6. 20.7. 20.8. Features................................................................................................................................... 265 Block Diagram.......................................................................................................................... 266 Signal Description....................................................................................................................
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SAM D5x/E5x Family Data Sheet 24.4. 24.5. 24.6. 24.7. 24.8. 24.9. Signal Description.................................................................................................................... 478 Product Dependencies............................................................................................................. 479 Functional Description..............................................................................................................480 Programming Interface...............
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SAM D5x/E5x Family Data Sheet 29.2. 29.3. 29.4. 29.5. 29.6. 29.7. 29.8. Features................................................................................................................................... 811 Block Diagram.......................................................................................................................... 812 Signal Description....................................................................................................................
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SAM D5x/E5x Family Data Sheet 34.2. 34.3. 34.4. 34.5. 34.6. 34.7. 34.8. USART Features...................................................................................................................... 922 Block Diagram.......................................................................................................................... 923 Signal Description.................................................................................................................... 923 Product Dependencies...
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SAM D5x/E5x Family Data Sheet 38.8. Register Description............................................................................................................... 1136 39. CAN - Control Area Network............................................................................... 1204 39.1. 39.2. 39.3. 39.4. 39.5. 39.6. 39.7. 39.8. 39.9. Overview................................................................................................................................ 1204 Features..................
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SAM D5x/E5x Family Data Sheet 44. TRNG – True Random Number Generator..........................................................1574 44.1. 44.2. 44.3. 44.4. 44.5. 44.6. 44.7. 44.8. Overview................................................................................................................................ 1574 Features................................................................................................................................. 1574 Block Diagram.................................
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SAM D5x/E5x Family Data Sheet 48.7. Register Description............................................................................................................... 1729 49. TCC – Timer/Counter for Control Applications.................................................... 1799 49.1. 49.2. 49.3. 49.4. 49.5. 49.6. 49.7. 49.8. Overview................................................................................................................................ 1799 Features.................................
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SAM D5x/E5x Family Data Sheet 53.7. Register Summary..................................................................................................................1959 53.8. Register Description............................................................................................................... 1960 54. Electrical Characteristics at 85°C........................................................................ 1986 54.1. Disclaimer.................................................................
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SAM D5x/E5x Family Data Sheet 59.1. Introduction.............................................................................................................................2096 59.2. Power Supply......................................................................................................................... 2096 59.3. External Analog Reference Connections............................................................................... 2098 59.4. External Reset Circuit.................................
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SAM D5x/E5x Family Data Sheet Configuration Summary 1. Configuration Summary Table 1-1.
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SAM D5x/E5x Family Data Sheet Configuration Summary Table 1-2.
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SAM D5x/E5x Family Data Sheet Ordering Information 2. Ordering Information Figure 2-1.
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SAM D5x/E5x Family Data Sheet Block Diagram 3. Block Diagram The actual configuration may vary with device memory and number of pins. Refer to the Configuration Summary for details.
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SAM D5x/E5x Family Data Sheet Block Diagram Related Links 1. Configuration Summary © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Pinout 4. Pinout 4.1 48-Pin VQFN Package 48 47 46 45 44 43 42 41 40 39 38 37 PB03 PB02 PA31 PA30 VDDIO VSW GND VDDCORE RESETN PA27 PB23 PB22 Figure 4-1. 48-Pin VQFN(1) Package 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO GND PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA08 PA09 PA10 PA11 VDDIO GND PB10 PB11 PA12 PA13 PA14 PA15 13 14 15 16 17 18 19 20 21 22 23 24 PA00 PA01 PA02 PA03 GNDANA VDDANA PB08 PB09 PA04 PA05 PA06 PA07 Note: 1.
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SAM D5x/E5x Family Data Sheet Pinout 64-Pin TQFP and VQFN Package 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB03 PB02 PB01 PB00 PB31 PB30 PA31 PA30 VDDIO VSW GND VDDCORE RESETN PA27 PB23 PB22 Figure 4-2.
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SAM D5x/E5x Family Data Sheet Pinout 4.
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SAM D5x/E5x Family Data Sheet Pinout 100-Pin TQFP Package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB03 PB02 PB01 PB00 PB31 PB30 PA31 PA30 VDDIO VSW GND VDDCORE RESETN PA27 PC28 PC27 PC26 PC25 PC24 PB25 PB24 PB23 PB22 VDDIO GND Figure 4-3.
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SAM D5x/E5x Family Data Sheet Pinout 4.5 120-ball TFBGA Package Figure 4-4.
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SAM D5x/E5x Family Data Sheet Pinout 128-Pin TQFP Package 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 PB03 PB02 PB01 PB00 PC31 PC30 PB31 PB30 PA31 PA30 VDDIO VSW GNDIO VDDCORE RESETN PA27 PC28 PC27 PC26 PC25 PC24 VDDIO GND PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 VDDIO Figure 4-5.
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SAM D5x/E5x Family Data Sheet Signal Descriptions List 5. Signal Descriptions List The following table gives details on signal names classified by peripheral. Table 5-1.
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SAM D5x/E5x Family Data Sheet Signal Descriptions List ...........
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SAM D5x/E5x Family Data Sheet Signal Descriptions List ...........
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SAM D5x/E5x Family Data Sheet Signal Descriptions List ...........
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations 6. I/O Multiplexing and Considerations 6.1 Multiplexed Signals By default each pin is controlled by the PORT as a general purpose I/O, and alternatively it can be assigned a different peripheral functions. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to '1'.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations VQFN 48 TQFP/VQFN/WLCSP 64 TQFP 100 TFBGA 120 TQFP 128 ...........
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations TQFP 128 TQFP 100 TQFP/VQFN/WLCSP 64 VQFN 48 ...........
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations 41/D2 TQFP 100 TQFP 128 29 TQFP/VQFN/WLCSP 64 VQFN 48 ...........
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations VQFN 48 TQFP/VQFN/WLCSP 64 TQFP 100 TFBGA 120 TQFP 128 ...........
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations Table 6-2. Oscillator Pinout Oscillator Supply Signal I/O pin XOSC0 VDDIO XIN PA14 XOUT PA15 XIN PB22 XOUT PB23 XIN32 PA00 XOUT32 PA01 XOSC1 XOSC32K VDDIO VSWOUT Note: To guarantee the XOSC32K behavior in crystal mode, PC00 must be static. Table 6-3. XOSC32K Jitter Minimization 6.2.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations ...........continued 6.2.4 Signal Supply I/O pin SWO VDDIO PB30, PC27 Supply Controller Pinout The outputs of the Supply Controller (SUPC) are not mapped to the normal PORT functions. They are controlled by registers in the SUPC. Table 6-6. SUPC Pinout Signal I/O pin OUT0 PB01 OUT1 PB02 Note: If the RTC is enabled to use the pins shared with the SUPC, the RTC will have higher priority. 6.2.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations Table 6-8. SERCOM I²C Pinout Package Pin Count Supply I/O pins with I²C Support 128 VDDIOB PA08, PA09 VDDIO PA12, PA13, PA16, PA17, PA22, PA23, PD08, PD09 VDDIOB PA08, PA09 VDDIO PA12, PA13, PA16, PA17, PA22, PA23, PD08, PD09 VDDIOB PA08, PA09 VDDIO PA12, PA13, PA16, PA17, PA22, PA23 VDDIOB PA08, PA09 VDDIO PA12, PA13, PA16, PA17, PA22, PA23 VDDIO PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23 120 100 64 48 6.2.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations 6.2.8.1 SERCOM IOSET Configurations The following tables lists each IOSET Pins for each SERCOM instance. Table 6-10. SERCOM0 IO SET Configuration SERCOM Signal IOSET 1 PINs IOSET 2 PINs IOSET 3 PINs IOSET 4 PINs PAD0 PA08 PB24 PA04 PC17 PAD1 PA09 PB25 PA05 PC16 PAD2 PA10 PC24 PA06 PC18 PAD3 PA11 PC25 PA07 PC19 IOSET 3 PINs IOSET 4 PINs Table 6-11.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations Table 6-15. SERCOM5 IO SET Configuration SERCOM Signal IOSET 1 PINs IOSET 2 PINs IOSET 3 PINs IOSET 4 PINs IOSET 5 PINs IOSET 6 PINs PAD0 PB16 PA23 PA23 PA23 PB31 PB02 PAD1 PB17 PA22 PA22 PA22 PB30 PB03 PAD2 PB18 PA20 PA24 PB22 PB00 PB00 PAD3 PB19 PA21 PA25 PB23 PB01 PB01 Table 6-16.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations ...........continued I²S Signal 6.2.8.4 IOSET 1 PINs IOSET 2 PINs SCK0 PA10 PB16 SDO PA11 PA21 SDI PB10 PA22 FS1 PB11 PA23 SCK1 PB12 PB28 MCK1 PB13 PB29 TC IOSET Configurations The following tables lists each IOSET Pins for each TC instance. Table 6-20. TC0 IOSET Configuration TC Signal IOSET 1 PINs IOSET 2 PINs IOSET 3 PINs WO0 PA04 PA08 PB30 WO1 PA05 PA09 PB31 Table 6-21.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations Table 6-25. TC5 IOSET Configuration TC Signal IOSET 1 PINs IOSET 2 PINs IOSET 3 PINs WO0 PB10 PB14 PA24 WO1 PB11 PB15 PA25 IOSET 2 PINs IOSET 3 PINs Table 6-26. TC6 IOSET Configuration TC Signal IOSET 1 PINs WO0 PB16 PA30 PB02 WO1 PB03 PB17 PA31 IOSET 2 PINs IOSET 3 PINs Table 6-27. TC7 IOSET Configuration 6.2.8.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations ...........continued TCC Signal IOSET 1 PINs IOSET 2 PINs IOSET 3 PINs IOSET 4 PINs WO4 PA20 WO5 IOSET 5 PINs PB28 PA08 PC10 N/A(1) PA21 PB29 PA09 PC11 N/A(1) WO6 PA22 PA10 PC12 N/A(1) N/A(1) WO7 PA23 PA11 PC13 N/A(1) N/A(1) Note: 1. The signal is available, but the edges are not aligned wrt. the other signals as specified. Table 6-30.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations 6.2.9 GPIO Clusters Table 6-34.
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SAM D5x/E5x Family Data Sheet I/O Multiplexing and Considerations ...........
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SAM D5x/E5x Family Data Sheet Power Supply and Start-Up ... 7. Power Supply and Start-Up Considerations 7.1 Power Domain Overview VDDIOB BAT (PB[3]) VDDANA PD[21:20] PC[31:10] PB[31:10] PD[12:8] PA[27:12] PA[31:30] VDDIO VSW GND VDDCORE GNDANA VDDANA Figure 7-1.
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SAM D5x/E5x Family Data Sheet Power Supply and Start-Up ... • VDDCORE – Serves as the internal voltage regulator output in linear mode, depending on the powering configuration. It powers the VSW core power domain and the VDDBU backup domain, memories, peripherals, DFLL48M, FDPLL200M, and RAMs. Voltage is 1.2V typical. • The Automatic Power Switch is a configurable switch that selects between VDD and VBAT as supply for the internal output VSWOUT, see the figure in 7.1 Power Domain Overview.
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SAM D5x/E5x Family Data Sheet Power Supply and Start-Up ... Figure 7-3. Power Supply Connection for Switching/Linear Mode DEVICE Main Supply VBAT (PB03) VDDANA (1.71V — 3.63V) VDDIO VSW VDDCORE GND GNDANA Figure 7-4. Power Supply Connection for Battery Backup DEVICE Main Supply VBAT (PB03) VDDANA (1.71V — 3.63V) VDDIO VSW VDDCORE GND GNDANA 7.2.4 Power-Up Sequence 7.2.4.1 Supply Order VDDIO and VDDANA must have the same supply sequence, and must be connected together.
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SAM D5x/E5x Family Data Sheet Power Supply and Start-Up ... 18. PM – Power Manager 7.3.1 Starting of Internal Regulator After power-up, the device is set to its initial state and kept in Reset, until the power has stabilized throughout the device. The internal regulator provides VDDCORE. Once the external voltage VDDIO/VDDANA and VDDCORE reach a stable value, the internal Reset is released. Related Links 18. PM – Power Manager 7.3.
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SAM D5x/E5x Family Data Sheet Power Supply and Start-Up ... 7.4.2 Power-On Reset on the main supply VDD (VDDANA/VDDIO) The Main supply VDD (VDDANA/VDDIO) is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If VDD goes below the threshold voltage, all I/Os supplied by VDDIO are reset. 7.4.3 Brown-Out Detector on VSWOUT/VBAT BOD33 monitors VSWOUT or VBAT depending on configuration. Related Links 19. SUPC – Supply Controller 7.4.
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SAM D5x/E5x Family Data Sheet Product Memory Mapping Overview 8. Product Memory Mapping Overview Figure 8-1.
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SAM D5x/E5x Family Data Sheet Product Memory Mapping Overview Related Links 9. Memories © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Memories 9. Memories 9.1 Embedded Memories • Internal high-speed Flash with Read-While-Write (RWW) capability on a section of the array • Internal high-speed RAM, single-cycle access at full speed • Internal backup RAM, single-cycle access at full speed 9.2 Physical Memory Map The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot.
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SAM D5x/E5x Family Data Sheet Memories 9.3 SRAM Memory Configuration Retention Depending on the application and power budget needs, part of the system memory can be retained in Standby or Hibernate sleep modes. The amount of the SRAM retained in this mode is software selectable, by writing the RAMCFG bits in the Power Manager Standby Configuration register and Hibernate Configuration register respectively (STDBYCFG.RAMCFG and HIBCFG.RAMCFG).
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SAM D5x/E5x Family Data Sheet Memories Figure 9-2. Memory with RAM Error Correction SAME54x20 SAME54x19 256KB 192KB Error Correction Error Correction 128KB 96KB 32KB 0x20000000 0KB Note: If the ECC is used, full SRAM retention must be enabled. CoreSight ETB Connection When enabled, the bottom 32 KB system memory space is reserved for CoreSight ETB debug usage. The figure below shows an example where both ECC and CoreSight ETB are enabled. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Memories Figure 9-3. Memory with ECC and CoreSight ETB SAME54x20 SAME54x19 256KB 192KB Error Correction Error Correction 128KB 96KB 32KB CoreSight ETB CoreSight ETB 0x20000000 9.4 0KB NVM User Page Mapping The NVM User Page can be read at address 0x00804000. The size of the NVM User Page is 512 Bytes. The first eight 32-bit words (32 Bytes) of the Non Volatile Memory (NVM) User Page contain calibration data that are automatically read at device power on.
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SAM D5x/E5x Family Data Sheet Memories ...........continued Bit Pos. Name Usage Related Peripheral Register Default Values 25:15 BOD12 Calibration Factory settings - do not change.(1) Parameters - 29:26 NVM BOOT NVM Bootloader Size 0xF 31:30 Reserved Factory settings - do not change.
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SAM D5x/E5x Family Data Sheet Memories 20.8.2 CONFIG 20.8.3 EWCTRL 45.6.3.1 Device Temperature Measurement 9.5 NVM Software Calibration Area Mapping The NVM Software Calibration Area contains calibration data that are determined and written during production test. These calibration values should be read by the application software and written back to the corresponding register. The NVM Software Calibration Area can be read at address 0x00800080. The NVM Software Calibration Area can not be written.
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SAM D5x/E5x Family Data Sheet Memories Table 9-4. NVM Software Calibration Area Mapping - Temperature Calibration Parameters Bit Position Name Description 7:0 TLI Integer part of calibration temperature TL 11:8 TLD Decimal part of calibration temperature TL 19:12 THI Integer part of calibration temperature TH 23:20 THD Decimal part of calibration temperature TH 39:24 Reserved Reserved for future use. 51:40 VPL Temperature calibration parameters.
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SAM D5x/E5x Family Data Sheet Processor and Architecture 10. Processor and Architecture 10.1 Cortex M4 Processor ™ The ARM®Cortex -M4 processor is a high performance 32-bit processor designed for the microcontroller market.
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SAM D5x/E5x Family Data Sheet Processor and Architecture 10.1.2 Integrated Configurable Debug The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Features Cortex-M4 Options SAM D5x/E5x Configuration Debug support level 0 = No debug. No DAP, breakpoints, watchpoints, Flash patch, or halting debug. 3 = Full debug plus DWT data matching. 1 = Minimum debug. Two breakpoints, one watchpoint, no Flash patch. 2 = Full debug minus DWT data matching. 3 = Full debug plus DWT data matching. Trace support level 0 = No trace. No ETM, ITM or DWT triggers and counters.
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SAM D5x/E5x Family Data Sheet Processor and Architecture Address Core Peripheral 0xE000E008-0xE000E00F System control block 0xE000E010-0xE000E01F System timer 0xE000E100-0xE000E4EF Nested Vectored Interrupt Controller 0xE000ED00-0xE000ED3F System control block 0xE000ED90-0xE000ED93 MPU Type Register 0xE000ED90-0xE000EDB8 Memory Protection Unit 0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller 0xE000EF30-0xE000EF44 Floating Point Unit Related Links 8.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line RTC - Real-Time Counter CMP A 0 11 CMP A 1 CMP A 2 CMP A 3 OVF A PER A 0 PER A 1 PER A 2 PER A 3 PER A 4 PER A 5 PER A 6 PER A 7 TAMPER A EIC - External Interrupt Controller FREQM - Frequency Meter © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line NVMCTRL - Non-Volatile Memory Controller(1) 0 29 1 2 3 4 5 6 7 8 30 9 10 DMAC - Direct Memory Access Controller SUSP 0 31 TCMPL 0 TERR 0 SUSP 1 32 TCMPL 1 TERR 1 SUSP 2 33 TCMPL 2 TERR 2 SUSP 3 34 TCMPL 3 TERR 3 SUSP 4..31 35 TCMPL 4..31 TERR 4..31 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line EVSYS - Event System Interface EVD 0 36 OVR 0 EVD 1 37 OVR 1 EVD 2 38 OVR 2 EVD 3 39 OVR 3 EVD 4..11 40 OVR 4..11 PAC - Peripheral Access Controller ERR 41 RAM ECC 0 45 1 SERCOM0 - Serial Communication Interface 0(1) 0 46 1 47 2 48 3 49 4 5 7 SERCOM1 - Serial Communication Interface 1(1) 0 50 1 51 2 52 3 53 4 5 7 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line SERCOM2 - Serial Communication Interface 2(1) 0 54 1 55 2 56 3 57 4 5 7 SERCOM3 - Serial Communication Interface 3(1) 0 58 1 59 2 60 3 61 4 5 7 SERCOM4 - Serial Communication Interface 4(1) 0 62 1 63 2 64 3 65 4 5 7 SERCOM5 - Serial Communication Interface 5(1) 0 66 1 67 2 68 3 69 4 5 7 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line SERCOM6 - Serial Communication Interface 6(1) 0 70 1 71 2 72 3 73 4 5 7 SERCOM7 - Serial Communication Interface 7(1) 0 74 1 75 2 76 3 77 4 5 7 CAN0 - Control Area Network 0 LINE 0 78 LINE 1 CAN1 - Control Area Network 1 LINE 0 79 LINE 1 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line USB - Universal Serial Bus EORSM DNRSM 80 EORST RST LPM DCONN LPMSUSP DDISC MSOF RAMACER RXSTP TXSTP 0..7 STALL0 STALL 0..7 STALL1 0..7 SUSPEND TRFAIL0 TRFAIL 0..7 TRFAIL1 PERR 0..7 UPRSM WAKEUP GMAC - Ethernet MAC SOF HSOF 81 TRCPT0 0..7 82 TRCPT1 0..7 83 GMAC 84 WOL © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line TCC0 - Timer Counter Control 0 CNT A 85 DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A TCC1 - Timer Counter Control 1 MC 0 86 MC 1 87 MC 2 88 MC 3 89 MC 4 90 MC 5 91 CNT A 92 DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line TCC2 - Timer Counter Control 2 CNT A 97 DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A TCC3 - Timer Counter Control 3 MC 0 98 MC 1 99 MC 2 100 CNT A 101 DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued Module Source Line TCC4 - Timer Counter Control 4 CNT A 104 DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A TC0 - Basic Timer Counter 0 MC 0 105 MC 1 106 ERR A 107 MC 0 MC 1 OVF TC1 - Basic Timer Counter 1 ERR A 108 MC 0 MC 1 OVF TC2 - Basic Timer Counter 2 ERR A 109 MC 0 MC 1 OVF TC3 - Basic Timer Counter 3 ERR A 110 MC 0 MC 1 OVF © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........
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SAM D5x/E5x Family Data Sheet Processor and Architecture 10.3 High-Speed Bus System 10.3.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued High-Speed Bus Matrix Masters Master ID ICM - Integrity Check Monitor 6 DSU - Device Service Unit 7 Table 10-2. High-Speed Bus Matrix Slaves 10.3.
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SAM D5x/E5x Family Data Sheet Processor and Architecture If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of one cycle for the RAM access. The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the tables below for details.
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SAM D5x/E5x Family Data Sheet Processor and Architecture ...........continued SRAM Port Connection Port ID Connection Type QoS default QoS GMAC - Ethernet MAC 12 Direct STATIC-2 0x2 USB - Universal Serial Bus Configuration Access 13 Direct IPQOSCTRL.CQOS 0x3 USB - Universal Serial Bus - Data Access 13 Direct IPQOSCTRL.DQOS 0x3 Note: 1. Using 32-bit access only. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11. 11.1 CMCC - Cortex M Cache Controller Overview The Cortex M Cache Controller provides an L1 cache to the Cortex M CPU. The CMCC sits transparently between the CPU and the cache leading to improved performance. The CMCC interfaces with the CPU through the AHB, and is connected to the APB bus interface for its configuration. 11.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.3 Block Diagram Figure 11-1. CMCC Block Diagram CM4F Cortex M Interface Cache Controller METADATA RAM RAM Interface APB interface DATA RAM Registers Interface TAG RAM Memory Interface High-Speed Bus Matrix Figure 11-2. CMCC Organization Line ‘n’ Base Address + 0x00000000 WAY 0 Base Address + 0x00000400 WAY 1 Base Address + 0x00000800 Line 0 Line 1 Line 2 Line 3 Line 4 ... ….. …….
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.4 Signal Description Not applicable. 11.5 Product Dependencies Not applicable. 11.5.1 I/O Lines Not applicable. 11.5.2 Power Management The CMCC will continue to function as long as the CPU is not sleeping and CMCC is enabled. 11.5.3 Clocks Not applicable. 11.5.4 DMA Not applicable. 11.5.5 Interrupts Not applicable. 11.5.6 Events Not applicable. 11.5.7 Debug Operation When the CPU is halted in debug mode, the CMCC is halted.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.6.3 Change Cache Size It is possible to change the cache size by writing to the Cache Size Configured By Software bits in the Cache Configuration register (CFG.CSIZESW). Use the following sequence to change the cache size: • Disable the CMCC controller by writing a zero to the Cache Controller Enable bit in the Cache Control register (CTRL.CEN=0).
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.6.7 Tightly Coupled Memory Users can use a part of the cache as Tightly Coupled Memory (TCM). The cache size is determined by the Cache Size Configuration by Software bits in the Cache Configuration register (CFG.CSIZESW). The relation between cache and TCM is as given below: TCM size = maximum Cache size - configured Cache size. The TCM start address can be obtained from the product memory mapping.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.6.9 Cache Performance Monitoring The Cortex M cache controller includes a programmable monitor/32-bit counter. The monitor can be configured to count the number of clock cycles, the number of data hit or the number of instruction hit. It is important to know that the Cortex-M4 processor prefetches instructions ahead of execution.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.8 RAM Properties The following table shows the different access properties of the three RAM blocks, according the different modes described in the previous chapters. Table 11-2.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.9 Offset Register Summary Name Bit Pos. 7:0 0x00 TYPE LCKDOWN WAYNUM[1:0] RRP 15:8 LRUP RANDP CLSIZE[2:0] GCLK AP CSIZE[2:0] 23:16 31:24 7:0 0x04 CFG CSIZESW[2:0] DCDIS ICDIS 15:8 23:16 31:24 7:0 0x08 CTRL CEN 15:8 23:16 31:24 7:0 0x0C SR CSTS 15:8 23:16 31:24 7:0 0x10 LCKWAY LCKWAY[3:0] 15:8 23:16 31:24 0x14 ...
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller ...........continued Offset 0x34 11.10 Name MSR Bit Pos. 7:0 EVENT_CNT[7:0] 15:8 EVENT_CNT[15:8] 23:16 EVENT_CNT[23:16] 31:24 EVENT_CNT[31:24] Register Description © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller Bits 6:5 – WAYNUM[1:0] Number of Way This bit field configures the mapping of the cache. Value Name Description 0x0 DMAPPED Direct Mapped Cache 0x1 ARCH2WAY 2-WAY set associative 0x2 ARCH4WAY 4-WAY set associative 0x3 ARCH8WAY 8-WAY set associative Bit 4 – RRP Round Robin Policy Supported Writing a '0' to this bit disables Round Robin Policy. Writing a '1' to this bit enables Round Robin Policy.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.2 Cache Configuration Name: Offset: Reset: Property: Bit CFG 0x04 0x00000020 R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 Access Reset Bit Access Reset Bit Access Reset Bit CSIZESW[2:0] Access Reset 2 1 DCDIS ICDIS R/W R/W R/W R/W R/W 0 1 0 0 0 Bits 6:4 – CSIZESW[2:0] Cache Size Configured by Software This field configures the cache size.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller Writing a '1' to this bit disables instruction caching. Value Description 0 Instruction caching is enabled. 1 Instruction caching is disabled. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.3 Cache Control Name: Offset: Reset: Property: Bit CTRL 0x08 0x00000000 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 CEN Access W Reset 0 Bit 0 – CEN Cache Controller Enable Writing a '0' to this bit disables the CMCC. Writing a '1' to this bit enables the CMCC. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.4 Cache Status Name: Offset: Reset: Property: Bit SR 0x0C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 CSTS Access R Reset 0 Bit 0 – CSTS Cache Controller Status Writing to this bit has no effect. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.5 Cache Lock per Way Name: Offset: Reset: Property: Bit LCKWAY 0x10 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit LCKWAY[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – LCKWAY[3:0] Lockdown Way Register This field selects which way is locked. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.6 Cache Maintenance 0 Name: Offset: Reset: Property: Bit MAINT0 0x20 0x00000000 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 INVALL Access W Reset 0 Bit 0 – INVALL Cache Controller Invalidate All Writing a '0' to this bit has no effect. Writing a '1' to this bit invalidates all cache entries.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.8 Cache Monitor Configuration Name: Offset: Reset: Property: Bit MCFG 0x28 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 MODE[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – MODE[1:0] Cache Controller Monitor Counter Mode This field selects the type of data monitored.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.9 Cache Monitor Enable Name: Offset: Reset: Property: Bit MEN 0x2C 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 MENABLE Access R/W Reset 0 Bit 0 – MENABLE Cache Controller Monitor Enable Writing a '0' to this bit disables the monitor counter.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.10 Cache Monitor Control Name: Offset: Reset: Property: Bit MCTRL 0x30 0x00000000 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 SWRST Access W Reset 0 Bit 0 – SWRST Cache Controller Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the event counter register.
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SAM D5x/E5x Family Data Sheet CMCC - Cortex M Cache Controller 11.10.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12. DSU - Device Service Unit 12.1 Overview The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU Reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components within the system.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.3 Block Diagram Figure 12-1. DSU Block Diagram DSU RESET SWCLK debugger_present DEBUGGER PROBE INTERFACE DMA request cpu_reset_extension CPU DAP AHB-AP DAP SECURITY FILTER DBG DMA NVMCTRL S S CORESIGHT ROM PORT M CRC-32 SWDIO MBIST M HIGH-SPEED BUS MATRIX CHIP ERASE 12.4 Signal Description The DSU uses three signals to function.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit Related Links 18. PM – Power Manager 12.5.3 Clocks The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main Clock Controller. Related Links 18. PM – Power Manager 15. MCLK – Main Clock 15.6.2.6 Peripheral Clock Masking 12.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit • Debugger probe detection For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification. 12.6.2 CPU Reset Extension “CPU Reset extension” refers to the extension of the Reset phase of the CPU core after the external Reset is released. This ensures that the CPU is not executing code at start-up while a debugger is connects to the system. The debugger is detected on a RESET release event when SWCLK is low.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit Figure 12-3. Hot-Plugging Detection Timing Diagram SWCLK RESET CPU_STATE reset running Hot-Plugging The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security bit.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.8 3. 2.3. Erases the lock row, removing the NVMCTRL security bit protection. Check for completion by polling STATUSA.DONE (read as '1' when completed). 4. Reset the device to let the NVMCTRL update the fuses. Programming Programming the Flash or RAM memories is only possible when the device is not protected by the NVMCTRL security bit. The programming procedure is as follows: 1. At power-up, RESET is driven low by a debugger.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100: • The first 0x100 bytes form the internal address range • The next 0x100 bytes form the external address range When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x2000.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.10 Device Identification Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device. 12.10.1 CoreSight Identification A system-level ARM® CoreSight™ ROM table is present in the device to identify the vendor and the chip identification method.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.11 Functional Description 12.11.1 Principle of Operation The DSU provides memory services, such as CRC32 or MBIST that require almost the same interface. Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured first; then a command can be issued by writing the Control register. When a command is ongoing, other commands are discarded until the current operation is completed.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 (reversed representation). 12.11.3.1 Starting CRC32 Calculation CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the size of the memory range into the Length register (LENGTH). Both must be wordaligned.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit trig on DCCx register empty. Writing a 1 to this bit will configure the DMA request to trig on DCCx register full. 12.11.6 Testing of On-Board Memories MBIST The DSU implements a feature for automatic testing of memory, also known as MBIST (memory built-in self test). This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external address range when the device is protected by the NVMCTRL security bit.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 4. Locating Faults If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error. The position of the failing bit can be found by reading the following registers: – ADDR: Address of the word containing the failing bit – DATA: contains data to identify which bit failed, and during which phase of the test it failed.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit Related Links 25. NVMCTRL – Nonvolatile Memory Controller 8. Product Memory Mapping Overview 12.11.7 System Services Availability when Accessed Externally and Device is Protected External access: Access performed in the DSU address offset 0x200-0x1FFF range. Internal access: Access performed in the DSU address offset 0x000-0x100 range. Table 12-6.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.12 Register Summary Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit ...........continued Offset Name Bit Pos. 0xF8 ... Reserved 0x0FFF 7:0 0x1000 ENTRY0 15:8 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 7:0 0x1004 0x1008 ENTRY1 END 15:8 FMT EPRES FMT EPRES ADDOFF[3:0] ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 7:0 END[7:0] 15:8 END[15:8] 23:16 END[23:16] 31:24 END[31:24] 0x100C ...
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit ...........continued Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.1 Control Name: Offset: Reset: Property: Bit 7 CTRL 0x0000 0x00 PAC Write-Protection 6 5 4 3 2 1 0 CE MBIST CRC SWRST Access W W W W Reset 0 0 0 0 Bit 4 – CE Chip-Erase Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the Chip-Erase operation. Bit 3 – MBIST Memory Built-In Self-Test Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the memory BIST algorithm.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.2 Status A Name: Offset: Reset: Property: Bit 7 STATUSA 0x0001 0x00 PAC Write Protection 6 Access 5 4 3 2 1 0 PERR FAIL BERR CRSTEXT DONE R/W R/W R/W R/W R/W 0 0 0 0 0 Reset Bit 4 – PERR Protection Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Protection Error bit. This bit is set when a command that is not allowed in Protected state is issued.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.3 Status B Name: Offset: Reset: Property: Bit 7 STATUSB 0x0002 0x0x PAC Write-Protection 6 5 4 3 2 1 0 CELCK HPE DCCD1 DCCD0 DBGPRES PROT Access R R R R R R Reset 0 0 0 0 x x Bit 5 – CELCK Chip Erase Locked Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when Chip Erase is locked. This bit is cleared when Chip Erase is unlocked.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.7 Debug Communication Channel x Name: Offset: Reset: Property: Bit DCC 0x10 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.8 Device Identification Name: Offset: Property: DID 0x0018 PAC Write Protection The information in this register is related to the Ordering Information.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 2. Ordering Information © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.10 Device Configuration Name: Offset: Reset: Property: Bit 31 DCFG 0xF0 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.11 CoreSight ROM Table Entry x Name: Offset: Reset: Property: ENTRY 0x1000 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.13 CoreSight ROM Table Memory Type Name: Offset: Reset: Property: Bit MEMTYPE 0x1FCC 0x0000000x - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 SMEMP Access R Reset x Bit 0 – SMEMP System Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.15 Peripheral Identification 7 Name: Offset: Reset: Property: Bit PID7 0x1FDC 0x00000000 Read-Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.16 Peripheral Identification 6 Name: Offset: Reset: Property: Bit PID6 0x1FD8 0x00000000 Read-Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.17 Peripheral Identification 5 Name: Offset: Reset: Property: Bit PID5 0x1FD4 0x00000000 Read-Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.20 Peripheral Identification 2 Name: Offset: Reset: Property: Bit PID2 0x1FE8 0x00000009 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit REVISION[3:0] JEPU JEPIDCH[2:0] Access R R R R R R R R Reset 0 0 0 0 1 0 0 1 Bits 7:4 – REVISION[3:0] Revision Number Revision of the peripheral.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.21 Peripheral Identification 3 Name: Offset: Reset: Property: Bit PID3 0x1FEC 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit REVAND[3:0] CUSMOD[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – REVAND[3:0] Revision Number These bits will always return 0x0 when read.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.22 Component Identification 0 Name: Offset: Reset: Property: Bit CID0 0x1FF0 0x0000000D - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit PREAMBLEB0[7:0] Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0 These bits will always return 0x0000000D when read.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.24 Component Identification 2 Name: Offset: Reset: Property: Bit CID2 0x1FF8 0x00000005 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit PREAMBLEB2[7:0] Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2 These bits will always return 0x00000005 when read.
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SAM D5x/E5x Family Data Sheet DSU - Device Service Unit 12.13.25 Component Identification 3 Name: Offset: Reset: Property: Bit CID3 0x1FFC 0x000000B1 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit PREAMBLEB3[7:0] Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3 These bits will always return 0x000000B1 when read.
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SAM D5x/E5x Family Data Sheet Clock System 13. Clock System This chapter summarizes the clock distribution and terminology in the SAM D5x/E5x device. It does not explain every detail of its configuration. For in-depth documentation, see the respective peripherals descriptions and the Generic Clock documentation. Related Links 14. GCLK - Generic Clock Controller 15. MCLK – Main Clock Clock Distribution Figure 13-1.
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SAM D5x/E5x Family Data Sheet Clock System – Generic Clock Generators: These are programmable prescalers that can use any of the system clock sources as a time base. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is used by the Power Manager and the Main Clock (MCLK) module, which in turn generates synchronous clocks.
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SAM D5x/E5x Family Data Sheet Clock System 13.2 Synchronous and Asynchronous Clocks As the CPU and the peripherals can be in different clock domains, i.e. they are clocked from different clock sources and/or with different clock speeds, some peripheral accesses by the CPU need to be synchronized. In this case the peripheral includes a Synchronization Busy (SYNCBUSY) register that can be used to check if a sync operation is in progress. For a general description, see 13.3 Register Synchronization.
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SAM D5x/E5x Family Data Sheet Clock System Figure 13-3. Register Synchronization Overview Synchronous Domain (CLK_APB) Asynchronous Domain (GCLK) Non Sync’d reg Sync Sync Read-Sync’d reg Read-only register Sync Periperal Bus Write-Sync’d reg Write-only register R/W-Sync’d reg Sync SYNCBUSY Write-Sync’d reg R/W register INTFLAG 13.3.
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SAM D5x/E5x Family Data Sheet Clock System REGC (16-bit access) can be written without affecting REGA or REGB. If REGC is written to in two consecutive 8-bit accesses without waiting for synchronization, the second write attempt will be discarded and an error is generated through the PAC. A 32-bit access to offset 0x00 will write all three registers. Note that REGA, REGB and REGC can be updated at different times because of independent write synchronization. 13.3.
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SAM D5x/E5x Family Data Sheet Clock System 13.4 Enabling a Peripheral In order to enable a peripheral that is clocked by a Generic Clock, the following parts of the system needs to be configured: • A running Clock Source • A clock from the Generic Clock Generator must be configured to use one of the running Clock Sources, and the Generator must be enabled.
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SAM D5x/E5x Family Data Sheet Clock System 13.6 Power Consumption vs. Speed When targeting for either a low-power or a fast acting system, some considerations have to be taken into account due to the nature of the asynchronous clocking of the peripherals: If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14. GCLK - Generic Clock Controller 14.1 Overview Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic Clock controller (GCLK) features 12 Generic Clock Generators [11:0] that can provide a wide range of clock frequencies. Generators can be set to use different external and internal oscillators as source. The clock of each Generator can be divided.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller The GCLK block diagram is shown below: Figure 14-2.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.5.3 Clocks The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Main Clock Controller. Related Links 15.6.2.6 Peripheral Clock Masking 29. OSC32KCTRL – 32KHz Oscillators Controller 14.5.4 DMA Not applicable. 14.5.5 Interrupts Not applicable. 14.5.6 Events Not applicable. 14.5.7 Debug Operation When the CPU is halted in debug mode the GCLK continues normal operation.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 1. 2. The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set (GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator Control register (GENCTRLn). The Generic Clock for a peripheral must be configured by writing to the respective Peripheral Channel Control register (PCHCTRLm).
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.6.2.5 Disabling a Generator A Generator is disabled by writing a '0' to GENCTRLn.GENEN. When GENCTRLn.GENEN=0, the GCLK_GEN[n] clock is disabled and gated. 14.6.2.6 Selecting a Clock Source for the Generator Each Generator can individually select a clock source by setting the Source Select bit group in the Generator Control register (GENCTRLn.SRC).
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.6.3 Peripheral Clock Figure 14-4. Peripheral Clock 14.6.3.1 Enabling a Peripheral Clock Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRL.GEN). Any available Generator can be selected as clock source for each Peripheral Channel.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller There is one exception concerning the Generator 0. As it is used as GCLK_MAIN, it cannot be locked. It is reset by any Reset and will start up in a known configuration. The software reset (CTRLA.SWRST) can not unlock the registers. In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to '1' the peripheral channels are disabled (PCHCTRLm.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.6.5.3 Entering Standby Mode There may occur a delay when the device is put into Standby, until the power is turned off. This delay is caused by running Clock Generators: if the Run in Standby bit in the Generator Control register (GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned of properly. The duration of this verification is frequency-dependent. Related Links 18. PM – Power Manager 14.6.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 SWRST 0x01 ... Reserved 0x03 7:0 0x04 SYNCBUSY GENCTRL[5:0] SWRST 15:8 GENCTRL[11:6] 23:16 31:24 0x08 ... Reserved 0x1F 7:0 0x20 GENCTRL0 SRC[4:0] 15:8 RUNSTDBY DIVSEL 23:16 DIV[7:0] 31:24 DIV[15:8] OE OOV IDC GENEN IDC GENEN ... 7:0 0x4C GENCTRL11 SRC[4:0] 15:8 RUNSTDBY DIVSEL 23:16 DIV[7:0] 31:24 DIV[15:8] OE OOV 0x50 ...
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 14.6.6 Synchronization. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 2 1 0 SWRST Access R/W Reset 0 Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Setting this bit to 1 will reset all registers in the GCLK to their initial state after a Power Reset, except for generic clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to 1.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.8.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.8.3 Generator Control Name: Offset: Reset: Property: GENCTRLn 0x20 + n*0x04 [n=0..11] 0x00000106 PAC Write-Protection, Write-Synchronized GENCTRLn controls the settings of Generic Generator n (n=[11:0]).
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller Value 1 Description The Generator is kept running and output to its dedicated GCLK_IO pin during Standby mode. Bit 12 – DIVSEL Divide Selection This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller ...........
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller 14.8.4 Peripheral Channel Control Name: Offset: Reset: Property: PCHCTRLm 0x80 + m*0x04 [m=0..47] 0x00000000 PAC Write-Protection PCHTRLm controls the settings of Peripheral Channel number m (m=[47:0]).
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller Table 14-7. Generator Selection Value Description 0x0 Generic Clock Generator 0 0x1 Generic Clock Generator 1 0x2 Generic Clock Generator 2 0x3 Generic Clock Generator 3 0x4 Generic Clock Generator 4 0x5 Generic Clock Generator 5 0x6 Generic Clock Generator 6 0x7 Generic Clock Generator 7 0x8 Generic Clock Generator 8 0x9 Generic Clock Generator 9 0xA Generic Clock Generator 10 0xB Generic Clock Generator 11 Table 14-8.
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SAM D5x/E5x Family Data Sheet GCLK - Generic Clock Controller ...........continued index(m) Name Description 5 GCLK_FREQM_MSR FREQM Measure 6 GCLK_FREQM_REF FREQM Reference 7 GCLK_SERCOM0_CORE SERCOM0 Core 8 GCLK_SERCOM1_CORE SERCOM1 Core 9 GCLK_TC0, GCLK_TC1 TC0, TC1 10 GCLK_USB USB 22:11 GCLK_EVSYS[0..11] EVSYS[0..
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15. MCLK – Main Clock 15.1 Overview The Main Clock (MCLK) controls the synchronous clock generation of the device. Using a clock provided by the Generic Clock Module (GCLK_MAIN), the Main Clock Controller provides synchronous system clocks to the CPU and the modules connected to the AHBx and the APBx bus. The synchronous system clocks are divided into a number of clock domains.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.5.2 Power Management The MCLK will operate in all sleep modes if a synchronous clock is required in these modes. Related Links 18. PM – Power Manager 15.5.3 Clocks The MCLK bus clock (CLK_MCLK_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_MCLK_APB can be found in the Peripheral Clock Masking section. If this clock is disabled, it can only be re-enabled by a reset.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.5.7 Debug Operation When the CPU is halted in debug mode, the MCLK continues normal operation. In sleep mode, the clocks generated from the MCLK are kept running to allow the debugger accessing any module. As a consequence, power measurements are incorrect in debug mode. 15.5.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.6.2.4 Selecting the Synchronous Clock Division Ratio The main clock GCLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock Related Links 27. PAC - Peripheral Access Controller 15.6.2.6 Peripheral Clock Masking It is possible to disable/enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (APBxMASK) to '0'/'1'. The default state of the peripheral clocks is shown here. Table 15-1.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock ...........
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock ...........
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock individually by writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding clearing bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 INTENCLR 7:0 CKRDY 0x02 INTENSET 7:0 CKRDY 0x03 INTFLAG 7:0 0x04 HSDIV 7:0 DIV[7:0] 0x05 CPUDIV 7:0 DIV[7:0] CKRDY 0x06 ...
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.1 Control A Name: Offset: Reset: Property: CTRLA 0x00 0x00 PAC Write-Protection All bits in this register are reserved. Bit 7 6 5 4 3 2 1 0 Access Reset © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.2 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x01 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.3 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x02 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.4 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x03 0x01 – 6 5 4 3 2 1 0 CKRDY Access R/W Reset 1 Bit 0 – CKRDY Clock Ready This flag is cleared by writing a '1' to the flag. This flag is set when the synchronous CPU, APBx, and AHBx clocks have frequencies as indicated in the CLKCFG registers and will generate an interrupt if INTENCLR/SET.CKRDY is '1'. Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.5 High-Speed Clock Division Name: Offset: Reset: Bit 7 HSDIV 0x04 0x01 6 5 4 3 2 1 0 DIV[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 1 Bits 7:0 – DIV[7:0] HS Clock Division Factor These bits define the division ratio of the main clock prescaler related to the HS clock domain (HSDIV). Value Name Description 0x01 DIV1 Divide by 1 others Reserved © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.6 CPU Clock Division Name: Offset: Reset: Property: Bit CPUDIV 0x05 0x01 PAC Write-Protection 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 1 DIV[7:0] Access Reset Bits 7:0 – DIV[7:0] CPU Clock Division Factor These bits define the division ratio of the main clock prescaler related to the CPU clock domain (CPUDIV). To ensure correct operation, frequencies must be selected so that fHS ≥ fCPU (i.e.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock Value 0 1 Description The AHB clock for the ICM is stopped. The AHB clock for the ICM is enabled. Bits 17, 18 – CANn CANn AHB Clock Enable Value Description 0 The AHB clock for the CANn is stopped. 1 The AHB clock for the CANn is enabled. Bits 15, 16 – SDHCn SDHCn AHB Clock Enable Value Description 0 The AHB clock for the SDHCn is stopped. 1 The AHB clock for the SDHCn is enabled.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock Value 0 1 Description The AHB clock for the NVMCTRL is stopped. The AHB clock for the NVMCTRL is enabled. Bit 4 – DSU DSU AHB Clock Enable Value Description 0 The AHB clock for the DSU is stopped. 1 The AHB clock for the DSU is enabled. Bits 0, 1, 2, 3 – HPBn HPBn AHB Clock Enable Value Description 0 The AHB clock for the HPBn is stopped. 1 The AHB clock for the APBn is enabled. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock Value 0 1 Description The APBA clock for the RTC is stopped. The APBA clock for the RTC is enabled. Bit 8 – WDT WDT APBA Clock Enable Value Description 0 The APBA clock for the WDT is stopped. 1 The APBA clock for the WDT is enabled. Bit 7 – GCLK GCLK APBA Clock Enable Value Description 0 The APBA clock for the GCLK is stopped. 1 The APBA clock for the GCLK is enabled.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock Value 0 1 Description The APBB clock for the EVSYS is stopped. The APBB clock for the EVSYS is enabled. Bit 4 – PORT PORT APBB Clock Enable Value Description 0 The APBB clock for the PORT is stopped. 1 The APBB clock for the PORT is enabled. Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable Value Description 0 The APBB clock for the NVMCTRL is stopped. 1 The APBB clock for the NVMCTRL is enabled.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock Value 0 1 Bit 8 – AC Value 0 1 Description The APBC clock for the AES is stopped. The APBC clock for the AES is enabled. AC APBC Mask Clock Enable Description The APBC clock for the AC is stopped. The APBC clock for the AC is enabled. Bit 7 – PDEC PDEC APBC Mask Clock Enable Value Description 0 The APBC clock for the PDEC is stopped. 1 The APBC clock for the PDEC is enabled.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock 15.8.
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SAM D5x/E5x Family Data Sheet MCLK – Main Clock Value 0 1 Description The APBD clock for the TCn is stopped. The APBD clock for the TCn is enabled. Bit 4 – TCC4 TCC4 APBD Mask Clock Enable Value Description 0 The APBD clock for the TCC4 is stopped. 1 The APBD clock for the TCC4 is enabled. Bits 0, 1, 2, 3 – SERCOM SERCOMn APBD Mask Clock Enable Value Description 0 The APBD clock for the SERCOMn is stopped. 1 The APBD clock for the SERCOMn is enabled. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RSTC – Reset Controller 16. RSTC – Reset Controller 16.1 Overview The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the device to its initial state and allows the reset source to be identified by software. 16.
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SAM D5x/E5x Family Data Sheet RSTC – Reset Controller Related Links 6. I/O Multiplexing and Considerations 16.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 16.5.1 I/O Lines Not applicable. 16.5.2 Power Management The Reset Controller module is always on. 16.5.3 Clocks The RSTC bus clock (CLK_RSTC_APB) can be enabled and disabled in the Main Clock Controller. Related Links 15. MCLK – Main Clock 15.6.2.
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SAM D5x/E5x Family Data Sheet RSTC – Reset Controller 16.6.2 Basic Operation 16.6.2.1 Initialization After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source. 16.6.2.2 Enabling, Disabling, and Resetting The RSTC module is always enabled. 16.6.2.3 Reset Causes and Effects The latest Reset cause is available in RCAUSE register, and can be read during the application boot sequence in order to determine proper action.
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SAM D5x/E5x Family Data Sheet RSTC – Reset Controller Note: Refer to the Timing Characteristics section of the Electrical Characteristics chapter. Related Links 20. WDT – Watchdog Timer 19. SUPC – Supply Controller 19.6.3 Battery Backup Power Switch 16.6.3 Additional Features Not applicable. 16.6.4 DMA Operation Not applicable. 16.6.5 Interrupts Not applicable. 16.6.6 Events Not applicable. 16.6.7 Sleep Mode Operation The RSTC module is active in all sleep modes. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RSTC – Reset Controller 16.7 Register Summary Offset Name Bit Pos. 0x00 RCAUSE 7:0 BACKUP 7:0 HIB 0x01 Reserved 0x02 BKUPEXIT 16.8 SYST WDT EXT NVM BOD33 BOD12 BBPS RTC POR Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
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SAM D5x/E5x Family Data Sheet RSTC – Reset Controller 16.8.1 Reset Cause Name: Offset: Property: RCAUSE 0x00 – When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written to '0'. Bit 7 6 5 4 3 2 1 0 BACKUP SYST WDT EXT NVM BOD33 BOD12 POR Access R R R R R R R R Reset x x x x x x x x Bit 7 – BACKUP Backup Reset This bit is set if either a Backup or Hibernate Reset has occurred.
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SAM D5x/E5x Family Data Sheet RSTC – Reset Controller 16.8.2 Backup Exit Source Name: Offset: Property: BKUPEXIT 0x02 – When either a Hibernate ora Backup Reset occurs, the bit corresponding to the exit condition is set to '1', the other bits are written to '0'. In some specific cases, the RTC and BBPS bits can be set together, e.g. when the device leaves the battery Backup Mode caused by a BBPS condition, and a RTC event was generated during the Battery Backup Mode period.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17. RAMECC – RAM Error Correction Code (ECC) 17.1 Overview Single bit error correction and dual bit error detection is available for RAM. 17.2 Features • Single bit correction and dual bit detection. • Error Interrupt. 17.3 Block Diagram Figure 17-1. RAMECC Block Diagram Write data ECC calculation 32 4x5 HADDR ERRADDR RAM Block 32 4x5 ECC logic ECCERR and ECCDUAL status ECCDIS 32 HRDATA 17.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.5.2 Power Management The RAMECC will continue to operate in any sleep mode where the selected source clock is running. The RAMECC’s interrupts can be used to wake up the device from sleep modes. Refer to the Power Manager chapter for details on the different sleep modes. Related Links 18. PM – Power Manager 17.5.3 Clocks The RAMECC bus clock is provided by the Main Clock Controller (MCLK) through the AHB-APB B bridge.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) If the RAMECC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 17.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: • Interrupt Flag Status and Clear (INTFLAG) register • Status (STATUS) register.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the ERRADDR register is read, the interrupt is disabled, or the RAMECC is reset. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.7 Register Summary Offset Name Bit Pos. 0x00 INTENCLR 7:0 DUALE SINGLEE 0x01 INTENSET 7:0 DUALE SINGLEE 0x02 INTFLAG 7:0 DUALE SINGLEE 0x03 STATUS 7:0 0x04 ERRADDR ECCDIS 7:0 ERRADDR[7:0] 15:8 ERRADDR[15:8] ERRADDR[16 23:16 :16] 31:24 0x08 ... Reserved 0x0E 0x0F 17.8 DBGCTRL 7:0 ECCELOG ECCDIS Register Description Registers can be 8, 16, or 32 bits wide.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.8.1 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x00 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.8.2 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x01 0x00 Write-Protected This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.8.3 Interrupt Flag Status and Clear Name: Offset: Reset: Bit 7 INTFLAG 0x02 0x00 6 5 4 3 2 Access Reset 1 0 DUALE SINGLEE R/W R/W 0 0 Bit 1 – DUALE Dual Bit ECC Error Interrupt This flag is set on the occurrence of a dual bit ECC error. Writing a '0' to this bit has no effect. Reading the ECCADDR register will clear the Dual Bit Error interrupt flag.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.8.4 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x03 0x00 Read Only, Write-Protected 6 5 4 3 2 1 0 ECCDIS Access R Reset 0 Bit 0 – ECCDIS ECC Disable This bit is fuse updated at startup. When enabled, the calculated ECC is written to RAM along with data. ECC correction and detection is enabled for reads. Value Description 0 ECC detection and correction is enabled. 1 ECC detection and correction is disabled.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.8.
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SAM D5x/E5x Family Data Sheet RAMECC – RAM Error Correction Code (ECC) 17.8.6 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0F 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 ECCELOG ECCDIS R/W R/W 0 0 Bit 1 – ECCELOG ECC Error Log When DBGCTRL.ECCDIS=0, This bit controls whether ECC errors are logged in the INTFLAG register. When DBGCTRL.ECCDIS=1, this bit has no meaning. Value Description 0 ECC errors for debugger reads are not logged.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18. PM – Power Manager Related Links 39.6.9 Sleep Mode Operation 18.1 Overview The Power Manager (PM) controls the sleep modes and the power domain gating of the device. Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. In active mode, the CPU is executing application code.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.5.1 I/O Lines Not applicable. 18.5.2 Clocks The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Main Clock module. If this clock is disabled, it can only be re-enabled by a system reset. 18.5.3 DMA Not applicable. 18.5.4 Interrupts The interrupt request line is connected to the interrupt controller. Using the PM interrupt requires the interrupt controller to be configured first. 18.5.5 Events Not applicable. 18.5.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.6 Functional Description 18.6.1 Terminology The following is a list of terms used to describe the Power Managemement features of this microcontroller. 18.6.1.1 Power Domains Leaving aside the supply domains, such as VDDANA and VDDIO, the device is split into these power domains: PDCORESW, PDBACKUP, PDSYSRAM and PDBKUPRAM. PDCORESW, PDSYSRAM and PDBKUPRAM are "switchable power domains".
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.6.3.3 Sleep Mode Controller A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (18.8.2 SLEEPCFG.SLEEPMODE) select the level of the sleep mode. Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG. 18.8.2 SLEEPCFG register due to bridges. Software must ensure that the 18.8.
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SAM D5x/E5x Family Data Sheet PM – Power Manager Note: 1. Running if requested by peripheral during SleepWalking 2. Running during SleepWalking 18.6.3.3.1 IDLE Mode IDLE mode allows power optimization with the fastest wake-up time. The CPU is stopped, and peripherals are still working. As in Active mode, the AHBx and APBx clocks for peripheral are still provided if requested. As the main clock source is still running, wake-up time is very fast.
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SAM D5x/E5x Family Data Sheet PM – Power Manager • Entering Hibernate or Backup mode: This mode is entered by executing the WFI instruction after selecting the Hibernate or Backup mode by writing the Sleep Mode bits in the Sleep Configuration register (18.8.2 SLEEPCFG.SLEEPMODE=HIBERNATE or =BACKUP). • Exiting Hibernate or Backup mode: is triggered when a Hibernate or Backup Reset is detected by the Reset Controller (RSTC).
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SAM D5x/E5x Family Data Sheet PM – Power Manager Table 18-3. Sleep Mode versus PDSYSRAM Power Domain State Overview Power Domain State Sleep Mode STDBYCFG HIBCFG.RA PDCORESW .
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SAM D5x/E5x Family Data Sheet PM – Power Manager ...........continued Power Domain State Sleep Mode HIBCFG.BR BKUPCFG. AMCFG BRAMCFG PDCORESW PDBACKUP PDBKUPRAM Off N/A off off off N/A 18.6.3.6 Regulators, RAMs, and NVM State in Sleep Mode By default, in standby sleep mode and backup sleep mode, the RAMs, NVM, and regulators are automatically set in low-power mode in order to reduce power consumption: • The RAM is in low-power mode if the device is in standby mode.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.6.4 Advanced Features 18.6.4.1 SleepWalking SleepWalking is the capability for a device to temporarily wake up clocks for a peripheral to perform a task without waking up the CPU from STANDBY sleep mode. At the end of the sleepwalking task, the device can either be woken p by an interrupt (from a peripheral involved in SleepWalking) or enter again into STANDBY sleep mode.
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SAM D5x/E5x Family Data Sheet PM – Power Manager As example, if the device is in standby sleep mode using the main voltage regulator (MAINVREG) in low power mode, the voltage level is lower than the one used in active mode. When the device wakes up, it takes a certain amount of time for the main regulator to transition to the voltage level corresponding to active mode, causing additional wake-up time. • Latency due to the CPU clock source wake-up time. • Latency due to the NVM memory access.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.6.7 Events Not applicable. 18.6.8 Sleep Mode Operation The Power Manager is always active. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 SLEEPCFG 7:0 IORET SLEEPMODE[2:0] 0x02 ... Reserved 0x03 0x04 INTENCLR 7:0 SLEEPRDY 0x05 INTENSET 7:0 SLEEPRDY 0x06 INTFLAG 7:0 SLEEPRDY 0x07 Reserved 0x08 STDBYCFG 7:0 0x09 HIBCFG 7:0 0x0A BKUPCFG 7:0 0x0B Reserved 0x0C PWSAKDLY 18.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection 6 5 4 3 2 1 0 IORET Access R/W Reset 0 Bit 2 – IORET I/O Retention Note: This bit is not reset by a hibernate or backup reset. When the IORET feature is used, the debugger access to the chip will not be allowed until the IORET bit is cleared after waking up from hibernate or backup sleep.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.2 Sleep Configuration Name: Offset: Reset: Property: Bit SLEEPCFG 0x01 0x02 PAC Write-Protection 7 6 5 4 3 2 1 0 SLEEPMODE[2:0] Access R/W R/W R/W 0 0 0 Reset Bits 2:0 – SLEEPMODE[2:0] Sleep Mode Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software has to make sure the SLEEPCFG register reads the wanted value before issuing WFI instruction.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.3 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x04 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 SLEEPRDY Access W Reset 0 Bit 0 – SLEEPRDY Sleep Mode Entry Ready Interrupt Enable Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.4 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x05 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 SLEEPRDY Access R/W Reset 0 Bit 0 – SLEEPRDY Sleep Mode Entry Ready Interrupt Enable Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.5 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x06 0x00 – 6 5 4 3 2 1 0 SLEEPRDY Access R/W Reset 0 Bit 0 – SLEEPRDY Sleep Mode Entry Ready This flag is set when the main very low power mode is ready and will generate an interrupt if INTENCLR/ SET.SLEEPRDY is '1'. See this Note for details. Writing a '1' to this bit has no effect. Writing a '1' to this bit clears the Performance Ready interrupt flag.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.6 Hibernate Configuration Name: Offset: Reset: Property: Bit 7 HIBCFG 0x09 0x00 PAC Write-Protection 6 5 4 3 2 1 BRAMCFG[1:0] Access Reset 0 RAMCFG[1:0] R/W R/W R/W R/W 0 0 0 0 Bits 3:2 – BRAMCFG[1:0] Backup RAM Configuration Value Name Description 0x0 RET In hibernate mode, all the backup RAM is retained. 0x1 PARTIAL In hibernate mode, only the first 4Kbytes of the backup RAM is retained.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.7 Standby Configuration Name: Offset: Reset: Property: Bit 7 STDBYCFG 0x08 0x00 PAC Write-Protection 6 5 4 3 2 1 FASTWKUP[1:0] Access Reset 0 RAMCFG[1:0] R/W R/W R/W R/W 0 0 0 0 Bits 5:4 – FASTWKUP[1:0] Fast Wakeup Value Name Description 0x0 NO Fast Wakeup is disabled. 0x1 NVM Fast Wakeup is enabled on NVM. 0x2 MAINVREG Fast Wakeup is enabled on the main voltage regulator (MAINVREG).
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.8 Backup Configuration Name: Offset: Reset: Property: Bit 7 BKUPCFG 0x0A 0x00 PAC Write-Protection 6 5 4 3 2 1 0 BRAMCFG[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – BRAMCFG[1:0] Backup RAM Configuration Value Name Description 0x0 RET In backup mode, all the backup RAM is retained. 0x1 PARTIAL In backup mode, only the first 4Kbytes of the backup RAM is retained. 0x2 OFF In backup mode, all the backup RAM is turned OFF. 0x3 Reserved Reserved.
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SAM D5x/E5x Family Data Sheet PM – Power Manager 18.8.9 Global Status Name: Offset: Reset: Property: Bit 7 PWSAKDLY 0xC [ID-00000a2f] 0x00 – 6 5 4 IGNACK 3 2 1 0 DLYVAL[6:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 – IGNACK Ignore Acknowledge signal Value Description 0 Power Switch acknowledge signal is taken into account when entering/exiting retention mode.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19. SUPC – Supply Controller 19.1 Overview The Supply Controller (SUPC) manages the voltage reference, power supply and supply monitoring of the device. It is also able to control two output pins. The SUPC controls the voltage regulators for the core (VDDCORE) and backup (VDDBU) domains. It sets the voltage regulators according to the sleep modes, or the user configuration.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller • Low power and sampled mode for low power applications with programmable sample frequency – Hysteresis value from Flash User Calibration – Monitor VDD or VBAT • 1.2V Brown-Out Detector (BOD12) • Output pins – Pin toggling on RTC event 19.3 Block Diagram Figure 19-1.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.5.1 I/O Lines I/O lines are configured by SUPC when the SUPC output (signal OUT) is enabled. The I/O lines need no user configuration. 19.5.2 Power Management The SUPC can operate in all sleep modes except backup sleep mode. BOD33 and Battery backup Power Switch can operate in backup mode. Related Links 18. PM – Power Manager 19.5.3 Clocks The SUPC bus clock (CLK_SUPC_APB) can be enabled and disabled in the Main Clock module.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Related Links 27. PAC - Peripheral Access Controller 19.5.9 Analog Connections Not applicable. 19.6 Functional Description 19.6.1 Voltage Regulator System Operation 19.6.1.1 Enabling, Disabling, and Resetting The LDO main voltage regulator is enabled after a power-reset. The main voltage regulator output supply level is automatically defined by the sleep mode selected in the Power Manager module. 19.6.1.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller The STATUS.VCORERDY bit is set to '1' as soon as the VDDCORE voltage has reached the target voltage. During voltage transition, STATUS.VCORERDY will read '0'. The Voltage Ready interrupt (VCORERDY) can be used to detect a 0-to-1 transition of STATUS.VCORERDY, see also 19.5.5 Interrupts. When entering the Standby, Hibernate, or Backup Sleep mode, and when no sleepwalking task is requested, the VDDCORE Voltage scaling control is not used. 19.6.1.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.6.2.4 Sleep Mode Operation The Voltage Reference output and the Temperature Sensor output behavior during sleep mode can be configured using the Run in Standby bit and the On Demand bit in the Voltage Reference register (VREF.RUNSTDBY, VREF.ONDEMAND), see the following table: Table 19-1. VREF Sleep Mode Operation VREF.ONDEMAND VREF.RUNSTDBY Voltage Reference Sleep behavior 19.6.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller – When BBPS.WAKEEN=0, the backup domain will be powered by Main Power, but the device will stay in backup mode. • For other exit condition (RTC): The device is kept in battery-powered backup mode until Main Power is restored to supply the device. Then, the backup domain will be powered by Main Power. 19.6.4 Output Pins The SUPC can drive two outputs. By writing a '1' to the corresponding Output Enable bit in the Backup Output Control register (BKOUT.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Power Supply Reset. When VDD crosses above the brown-out threshold level (BOD33.LEVEL), the device will leave battery backup mode and will wakeup from backup mode if the BBPS.WAKEEN bit is set. The BOD33 detection status can be read from the BOD33 Detection bit in the Status register (STATUS.BOD33DET). At start-up or at Power-On Reset (POR), the BOD33 register values are loaded from the NVM User Row. Related Links 9.4 NVM User Page Mapping 19.6.5.3.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller VCC VBOD RESET Hysteresis ON: VCC VBOD+ VBOD- RESET Enabling the BOD33 hysteresis by writing the Hysteresis bit field in the BOD33 register (BOD33.HYST) to a non-null value will add hysteresis to the BOD33 threshold level. The hysteresis functionality can be used in Sampling Mode. Related Links 9.4 NVM User Page Mapping 19.6.5.3.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller • • • • Voltage Regulator Ready (VREGRDY) asynchronous BOD33 Ready (BOD33RDY), synchronous BOD33 Detection (BOD33DET), asynchronous BOD33 Synchronization Ready (B33SRDY), synchronous Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.7 Offset 0x00 Register Summary Name INTENCLR Bit Pos.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.1 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x00 0x00000000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Writing a '1' to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt. Value Description 0 The BOD33 Synchronization Ready interrupt is disabled. 1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.2 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x04 0x00000000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Writing a '1' to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33 Synchronization Ready interrupt. Value Description 0 The BOD33 Synchronization Ready interrupt is disabled. 1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Bit 1 – BOD33DET BOD33 Detection This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (STATUS.BOD33DET) and will generate an interrupt request if INTENSET.BOD33DET=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Detection interrupt flag. Bit 0 – BOD33RDY BOD33 Ready This flag is cleared by writing a '1' to it.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Bit 0 – BOD33RDY BOD33 Ready The BOD33 can be enabled at start-up from NVM User Row. Value Description 0 BOD33 is not ready. 1 BOD33 is ready. Related Links 9.4 NVM User Page Mapping © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.5 3.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Name NODIV DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 Description Not divided: Sampling mode is OFF. Divide clock by 4 Divide clock by 8 Divide clock by 16 Divide clock by 32 Divide clock by 64 Divide clock by 128 Divide clock by 256 Bits 11:8 – HYST[3:0] BOD33 Hysteresis Voltage Value on VDD This field sets the hysteresis voltage value related to "BOD33 Threshold Level on VDD" field when the BOD33 monitors VDD.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller These bits are loaded from NVM User Row at start-up. This field is not synchronized. Value Name Description 0x0 NONE No action 0x1 RESET The BOD33 generates a reset 0x2 INT 0x3 BKUP- The BOD33 generates an interrupt The BOD33 puts the device in battery backup sleep mode. Bit 1 – ENABLE Enable This bit is loaded from NVM User Row at start-up. This bit is not enable-protected. Value Description 0 BOD33 is disabled. 1 BOD33 is enabled.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Bit 1 – ENABLE Must be set to 1. Related Links 9.4 NVM User Page Mapping © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller Bit 6 – RUNSTDBY Run In Standby The bit controls how the voltage reference behaves during standby sleep mode. Value Description 0 The voltage reference is halted during standby sleep mode. 1 The voltage reference is not stopped in standby sleep mode. If VREF.ONDEMAND=1, the voltage reference will be running when a peripheral is requesting it. If VREF.ONDEMAND=0, the voltage reference will always be running in standby sleep mode.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.
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SAM D5x/E5x Family Data Sheet SUPC – Supply Controller 19.8.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20. 20.1 WDT – Watchdog Timer Overview The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.3 Block Diagram Figure 20-1. WDT Block Diagram 0xA5 0 CLEAR OSC32KCTRL CLK_WDT_OSC COUNT PER/WINDOWS/EWOFFSET Early Warning Interrupt Reset 20.4 Signal Description Not applicable. 20.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 20.5.1 I/O Lines Not applicable. 20.5.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer The counter clock CLK_WDT_OSC is asynchronous to the bus clock (CLK_WDT_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 20.6.7 Synchronization for further details. Related Links 15.6.2.6 Peripheral Clock Masking 29. OSC32KCTRL – 32KHz Oscillators Controller 20.5.4 DMA Not applicable. 20.5.5 Interrupts The interrupt request line is connected to the interrupt controller.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer Table 20-1. WDT Operating Modes 20.6.2 CTRLA.ENABLE CTRLA.WEN Interrupt Enable Mode 0 x x Stopped 1 0 0 Normal mode 1 0 1 Normal mode with Early Warning interrupt 1 1 0 Window mode 1 1 1 Window mode with Early Warning interrupt Basic Operation 20.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the WDT is disabled (CTRLA.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer WDT will issue a system reset if a time-out occurs. This can be prevented by clearing the WDT at any time during the time-out period. The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register (CLEAR). Writing any other value than 0xA5 to CLEAR will issue an immediate system reset. There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s. By default, the early warning interrupt is disabled.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer Figure 20-3. Window-Mode Operation WDT Count Timely WDT Clear PER[3:0] = 0 Open WDT Timeout Early WDT Clear WINDOW[3:0] = 0 Closed Early Warning Interrupt System Reset t[ms] 5 10 15 20 TOWDTW 20.6.3 DMA Operation Not applicable. 20.6.4 Interrupts The WDT has the following interrupt source: 25 30 35 TOWDT • Early Warning (EW): Indicates that the counter is approaching the time-out condition. – This interrupt is an asynchronous wake-up source.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.6.7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following registers are synchronized when written: • • • • Enable bit in Control A register (CTRLA.ENABLE) Window Enable bit in Control A register (CTRLA.WEN) Always-On bit in control Control A (CTRLA.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer The user must take caution when programming the Early Warning Offset bits. If these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Consequently, the Early Warning interrupt will never be generated. In window mode, the Early Warning interrupt is generated at the start of the open window period.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 CONFIG 7:0 0x02 EWCTRL 7:0 ALWAYSON WEN WINDOW[3:0] ENABLE PER[3:0] EWOFFSET[3:0] 0x03 Reserved 0x04 INTENCLR 7:0 EW 0x05 INTENSET 7:0 EW 0x06 INTFLAG 7:0 EW 0x07 Reserved 7:0 0x08 SYNCBUSY 0x0C CLEAR CLEAR ALWAYSON WEN ENABLE 15:8 23:16 31:24 20.8 7:0 CLEAR[7:0] Register Description Registers can be 8, 16, or 32 bits wide.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.1 Control A Name: Offset: Reset: Property: Bit Access Reset 7 CTRLA 0x00 x initially determined from NVM User Row after reset PAC Write-Protection, Write-Synchronized 6 5 4 3 2 1 ALWAYSON WEN ENABLE R/W R/W R/W x x x 0 Bit 7 – ALWAYSON Always-On This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT will remain enabled until a power-on Reset is received.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.2 Configuration Name: Offset: Reset: Property: Bit CONFIG 0x01 x initially determined from NVM User Row after reset PAC Write-Protection 7 6 5 4 3 2 R/W x 1 0 R/W R/W R/W R/W R/W x x x x R/W R/W x x x WINDOW[3:0] Access Reset PER[3:0] Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1.024kHz CLK_WDT_OSC clock.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.3 Early Warning Control Name: Offset: Reset: Property: Bit 7 EWCTRL 0x02 x initially determined from NVM User Row after reset PAC Write-Protection 6 5 4 3 2 1 0 R/W R/W R/W R/W x x x x EWOFFSET[3:0] Access Reset Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and the generation of the Early Warning interrupt.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x04 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x05 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x06 0x00 N/A 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning This flag is cleared by writing a '1' to it. This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning interrupt flag.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.7 Synchronization Busy Name: Offset: Reset: Property: Bit SYNCBUSY 0x08 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 Access Reset Bit Access Reset Bit Access Reset Bit 4 3 2 1 CLEAR ALWAYSON WEN ENABLE Access R R R R Reset 0 0 0 0 Bit 4 – CLEAR Clear Synchronization Busy Value Description 0 Write synchronization of the CLEAR register is complete.
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SAM D5x/E5x Family Data Sheet WDT – Watchdog Timer 20.8.8 Clear Name: Offset: Reset: Property: CLEAR 0x0C 0x00 Write-Synchronized Bit 7 6 5 4 3 2 1 0 Access W W W W Reset 0 0 0 W W W W 0 0 0 0 0 CLEAR[7:0] Bits 7:0 – CLEAR[7:0] Watchdog Clear In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog Timer and the watchdog time-out period is restarted.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21. RTC – Real-Time Counter 21.1 Overview The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/ compare wake up, periodic wake up, or overflow wake up mechanisms, or from the wake inputs.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.3 Block Diagram Figure 21-1. RTC Block Diagram (Mode 0 — 32-Bit Counter) 0x00000000 MATCHCLR OSC32KCTRL CLK_RTC_OSC CLK_RTC_CNT PRESCALER OVF COUNT Periodic Events = CMPn = OVF = CMPn COMPn Figure 21-2. RTC Block Diagram (Mode 1 — 16-Bit Counter) 0x0000 OSC32KCTRL CLK_RTC_OSC PRESCALER Periodic Events CLK_RTC_CNT COUNT PER COMPn Figure 21-3.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.4 Signal Description Table 21-1. Signal Description Signal Description Type INn [n=0..4] Tamper Detection Input Digital input OUT Tamper Detection Output Digital output One signal can be mapped to one of several pins. Related Links 6. I/O Multiplexing and Considerations 21.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 21.5.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Related Links 22. DMAC – Direct Memory Access Controller 21.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupt requires the Interrupt Controller to be configured first. Related Links 10.2 Nested Vector Interrupt Controller 21.5.6 Events The events are connected to the Event System. Related Links 31. EVSYS – Event System 21.5.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.6.2 Basic Operation 21.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRLA.ENABLE=0): • • • • Operating Mode bits in the Control A register (CTRLA.MODE) Prescaler bits in the Control A register (CTRLA.PRESCALER) Clear on Match bit in the Control A register (CTRLA.MATCHCLR) Clock Representation bit in the Control A register (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter The counter value is continuously compared with the 32-bit Compare registers (COMPn, n=0–1). When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the next counter cycle when a compare match with COMPn occurs.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter (INTFLAG.ALARMn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a delay of 1s after the occurrence of alarm match. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm n Mask register (MASKn.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.6.5 Events The RTC can generate the following output events: • Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero. • Tamper (TAMPER): Generated on detection of valid signal on a tamper input pin or tamper event input. • Compare (CMPn): Indicates a match between the counter value and the compare register. • Alarm (ALARM): Indicates a match between the clock value and the alarm register.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter • • • • • • • • Counter Value register, COUNT Clock Value register, CLOCK Counter Period register, PER Compare n Value registers, COMPn Alarm n Value registers, ALARMn Frequency Correction register, FREQCORR Alarm n Mask register, MASKn The General Purpose n registers (GPn) The following registers are synchronized when read: • The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.6.8.2 Frequency Correction The RTC Frequency Correction module employs periodic counter corrections to compensate for a tooslow or too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1. The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1ppm steps.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter alarm, CTRLB.GPnEN must be written to zero and the associated COMPn/ALARMn must be written with the correct value. An example procedure to write the general purpose registers GP0 and GP1 is: 1. Wait for any ongoing write to COMP0 to complete (SYNCBUSY.COMP0 = 0). If the RTC is operating in Mode 1, wait for any ongoing write to COMP1 to complete as well (SYNCBUSY.COMP1 = 0). 2. Write CTRLB.GP0EN = 1 if GP0 is needed. 3. Write GP0 if needed. 4.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Separate debouncers are embedded for each external input. The debouncer for each input is enabled/ disabled with the Debounce Enable bits in the Tamper Control register (TAMPCTRL.DEBNCn). The debouncer configuration is fixed for all inputs as set by the Control B register (CTRLB). The debouncing period duration is configurable using the Debounce Frequency field in the Control B register (CTRLB.DEBF). The period is set for all debouncers (i.e.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Figure 21-5. Edge Detection with Debouncer Disabled CLK_RTC CLK_RTC_DEB IN NE PE NE PE NE PE OUT TAMLVL=0 CLK_RTC CLK_RTC_DEB IN NE PE NE PE NE PE OUT TAMLVL=1 Figure 21-6.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Figure 21-7. Edge Detection with Asynchronous Stability Debouncing CLK_RTC CLK_RTC_DEB IN PE NE PE NE PE NE Once a new edge is detected, ignore subsequent edges until input is stable for 4 consecutive CLK_RTC_DEB OUT TAMLVL=0 CLK_RTC CLK_RTC_DEB IN PE NE PE NE PE NE Once a new edge is detected, ignore subsequent edges until input is stable for 4 consecutive CLK_RTC_DEB OUT TAMLVL=1 Figure 21-8.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Related Links 21.3 Block Diagram 21.6.8.5.1 Timestamp 21.6.8.5.2 Active Layer Protection 21.6.8.5.1 Timestamp As part of tamper detection the RTC can capture the counter value (COUNT/CLOCK) into the TIMESTAMP register. Three CLK_RTC periods are required to detect the tampering condition and capture the value. The TIMESTAMP value can be read once the Tamper flag in the Interrupt Flag register (INTFLAG.TAMPER) is set.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.6.8.5 Tamper Detection © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.7 Register Summary - Mode 0 - 32-Bit Counter Offset Name 0x00 CTRLA 0x02 0x04 CTRLB EVCTRL Bit Pos.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter ...........continued Offset 0x40 0x44 0x48 0x4C Name GP0 GP1 GP2 GP3 Bit Pos. 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x50 ...
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter ...........continued Offset 0x88 0x8C 0x90 0x94 0x98 0x9C 21.8 Name BKUP2 BKUP3 BKUP4 BKUP5 BKUP6 BKUP7 Bit Pos.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.1 Control A in COUNT32 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0x6 0x7 0x8 0x9 0xA 0xB 0xC-0xF Name DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024 - Description CLK_RTC_CNT = GCLK_RTC/32 CLK_RTC_CNT = GCLK_RTC/64 CLK_RTC_CNT = GCLK_RTC/128 CLK_RTC_CNT = GCLK_RTC/256 CLK_RTC_CNT = GCLK_RTC/512 CLK_RTC_CNT = GCLK_RTC/1024 Reserved Bit 7 – MATCHCLR Clear on Match This bit defines if the counter is cleared or not on a match. This bit is not synchronized.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.2 Control B in COUNT32 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Bit 6 – RTCOUT RTC Output Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.3 Event Control in COUNT32 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0 1 Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.4 Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0) Name: Offset: Reset: Property: INTENCLR 0x08 0x0000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.5 Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0) Name: Offset: Reset: Property: INTENSET 0x0A 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.6 Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0) Name: Offset: Reset: Property: Bit Access Reset Bit Access Reset INTFLAG 0x0C 0x0000 - 15 14 OVF R/W 0 13 12 11 10 9 8 TAMPER CMP1 CMP0 R/W R/W R/W 0 0 0 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.7 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0E 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.8 Synchronization Busy in COUNT32 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0 1 Description Write synchronization for FREQCORR register is complete. Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.9 Frequency Correction Name: Offset: Reset: Property: Bit 7 FREQCORR 0x14 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 R/W R/W R/W R/W 0 0 0 0 SIGN Access Reset 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 VALUE[6:0] Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.10 Counter Value in COUNT32 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.11 Compare n Value in COUNT32 mode (CTRLA.MODE=0) Name: Offset: Reset: Property: Bit COMP 0x20 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.12 General Purpose n Name: Offset: Reset: Property: Bit GPn 0x40 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0x3 Name ACTL Description Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.15 Tamper ID Name: Offset: Reset: Bit 31 TAMPID 0x68 0x00000000 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Access Reset Bit Access Reset Bit Access Reset 4 3 2 1 0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.8.16 Backup n Name: Offset: Reset: Property: Bit BKUP 0x80 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.9 Register Summary - Mode 1 - 16-Bit Counter Offset Name 0x00 CTRLA 0x02 0x04 CTRLB EVCTRL Bit Pos.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter ...........continued Offset Name Bit Pos. 0x28 ... Reserved 0x3F 0x40 0x44 0x48 0x4C GP0 GP1 GP2 GP3 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x50 ...
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter ...........continued Offset 0x88 0x8C 0x90 0x94 0x98 0x9C 21.10 Name BKUP2 BKUP3 BKUP4 BKUP5 BKUP6 BKUP7 Bit Pos.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.1 Control A in COUNT16 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC-0xF Name DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024 - Description CLK_RTC_CNT = GCLK_RTC/4 CLK_RTC_CNT = GCLK_RTC/8 CLK_RTC_CNT = GCLK_RTC/16 CLK_RTC_CNT = GCLK_RTC/32 CLK_RTC_CNT = GCLK_RTC/64 CLK_RTC_CNT = GCLK_RTC/128 CLK_RTC_CNT = GCLK_RTC/256 CLK_RTC_CNT = GCLK_RTC/512 CLK_RTC_CNT = GCLK_RTC/1024 Reserved Bits 3:2 – MODE[1:0] Operating Mode This field defines the operating mode of the RT
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.2 Control B in COUNT16 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Bit 6 – RTCOUT RTC Output Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.3 Event Control in COUNT16 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0 1 Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.4 Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1) Name: Offset: Reset: Property: INTENCLR 0x08 0x0000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.5 Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1) Name: Offset: Reset: Property: INTENSET 0x0A 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.6 Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.7 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0E 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.8 Synchronization Busy in COUNT16 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0 1 Description Read/write synchronization for COUNT register is complete. Read/write synchronization for COUNT register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. 1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.9 Frequency Correction Name: Offset: Reset: Property: Bit 7 FREQCORR 0x14 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 R/W R/W R/W R/W 0 0 0 0 SIGN Access Reset 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 VALUE[6:0] Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.10 Counter Value in COUNT16 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.11 Counter Period in COUNT16 mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.12 Compare n Value in COUNT16 mode (CTRLA.MODE=1) Name: Offset: Reset: Property: Bit COMP 0x20 + n*0x02 [n=0..
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.13 General Purpose n Name: Offset: Reset: Property: Bit GPn 0x40 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0x3 Name ACTL Description Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.16 Tamper ID Name: Offset: Reset: Bit 31 TAMPID 0x68 0x00000000 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Access Reset Bit Access Reset Bit Access Reset 4 3 2 1 0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.10.17 Backup n Name: Offset: Reset: Property: Bit BKUP 0x80 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.11 Register Summary - Mode 2 - Clock/Calendar Offset Name 0x00 CTRLA 0x02 0x04 CTRLB EVCTRL Bit Pos.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter ...........continued Offset Name Bit Pos. 0x2C MASK1 7:0 SEL[2:0] 0x2D ... Reserved 0x3F 7:0 0x40 0x44 0x48 0x4C GP0 GP1 GP2 GP3 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x50 ...
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter ...........continued Offset 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 21.12 Name BKUP1 BKUP2 BKUP3 BKUP4 BKUP5 BKUP6 BKUP7 Bit Pos.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.1 Control A in Clock/Calendar mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0x6 0x7 0x8 0x9 0xA 0xB 0xC-0xF Name DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024 - Description CLK_RTC_CNT = GCLK_RTC/32 CLK_RTC_CNT = GCLK_RTC/64 CLK_RTC_CNT = GCLK_RTC/128 CLK_RTC_CNT = GCLK_RTC/256 CLK_RTC_CNT = GCLK_RTC/512 CLK_RTC_CNT = GCLK_RTC/1024 Reserved Bit 7 – MATCHCLR Clear on Match This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is disabled. This bit is not synchronized.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0 1 Description There is not reset operation ongoing The reset operation is ongoing © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.2 Control B in Clock/Calendar mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Bit 6 – RTCOUT RTC Out Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.3 Event Control in Clock/Calendar mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0 1 Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.4 Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2) Name: Offset: Reset: Property: INTENCLR 0x08 0x0000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.5 Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2) Name: Offset: Reset: Property: INTENSET 0x0A 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.6 Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.7 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0E 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.8 Synchronization Busy in Clock/Calendar mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0 1 Description Read/write synchronization for CLOCK register is complete. Read/write synchronization for CLOCK register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. 1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.9 Frequency Correction Name: Offset: Reset: Property: Bit 7 FREQCORR 0x14 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 R/W R/W R/W R/W 0 0 0 0 SIGN Access Reset 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 VALUE[6:0] Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.10 Clock Value in Clock/Calendar mode (CTRLA.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.11 Alarm n Value in Clock/Calendar mode (CTRLA.MODE=2) Name: Offset: Reset: Property: ALARM 0x20 + n*0x08 [n=0..1] 0x00000000 PAC Write-Protection, Write-Synchronized The 32-bit value of ALARMn is continuously compared with the 32-bit CLOCK value, based on the masking set by MASKn.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.12 Alarm n Mask in Clock/Calendar mode (CTRLA.MODE=2) Name: Offset: Reset: Property: Bit 7 MASK 0x24 + n*0x08 [n=0..1] 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 2 1 0 SEL[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – SEL[2:0] Alarm Mask Selection These bits define which bit groups of Alarm n are valid.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.13 General Purpose n Name: Offset: Reset: Property: Bit GPn 0x40 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter Value 0x3 Name ACTL Description Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.16 Tamper ID Name: Offset: Reset: Bit 31 TAMPID 0x68 0x00000000 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Access Reset Bit Access Reset Bit Access Reset 4 3 2 1 0 TAMPID4 TAMPID3 TAMPID2 TAMPID1 TAMPID0 R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet RTC – Real-Time Counter 21.12.17 Backup n Name: Offset: Reset: Property: Bit BKUP 0x80 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22. DMAC – Direct Memory Access Controller 22.1 Overview The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller • • • • • • • • • – Single transfer using one descriptor – Multi-buffer or circular buffer modes by linking multiple descriptors Up to 32channels – Enable 32 independent transfers – Automatic descriptor fetch for each channel – Suspend/resume operation support for each channel Flexible arbitration scheme – 4 configurable priority levels for each channel – Fixed or round-robin priority scheme within each priority level From 1 to 256
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.3 Block Diagram Figure 22-1. DMAC Block Diagram CPU Optional SRAM M HIGH SPEED BUS MATRIX S Data Transfer M Data Transfer Write-back Descriptor Fetch M S Event System S Peripheral AHB/APB Bridge DMAC Internal Architecture Master Interface DMA Channels Fifo Channel n n Fetch Engine Channel 0 Arbiter Active Channel Pre-Fetch Channel CRC Engine 22.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 15.6.2.6 Peripheral Clock Masking 22.5.4 DMA Not applicable. 22.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the interrupt controller to be configured first. Related Links 10.2 Nested Vector Interrupt Controller 22.5.6 Events The events are connected to the event system. 22.5.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Figure 22-2. DMA Transfer Sizes Link Enabled Beat transfer Link Enabled Burst transfer Link Enabled Block transfer DMA transaction • Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) • Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k beats.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller • Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register (CTRL.LVLENx=1) DMA Channel Initialization Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, as defined below: • DMA Channel Configuration: – The channel number of the DMA channel to configure must be written to the Channel Control A (CHCTRLA) register.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled: • The Channel Software Reset bit in the Channel Control A (CHCTRLA.SWRST) register The following CRC registers are enable-protected, that is, they can only be written when the CRC is disabled (CRCCTRL.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Figure 22-3.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller DMA channel being granted access to perform its next burst transfer. When the Active Channel has completed a burst transfer, the descriptor stored in the Pre-Fetch Channel is transferred to the Active Channel and a new burst will take place. When the descriptor stored in the Pre-Fetch Channel is transferred to the Active Channel, the corresponding PENDCH.PENDCHx will be cleared.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller channel number as shown in Static Priority Scheduling. When using the static scheme, there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. Figure 22-5. Static Priority Scheduling Lowest Channel Channel 0 Highest Priority . . . Channel x Channel x+1 . . .
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.6.2.5 Data Transmission Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as the active channel.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller The following figure shows an example where triggers are used with two linked block descriptors. Figure 22-7.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register (BTCTRL.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller �� = �� + �� • �� + 1 • 2�� where BTCTRL.STEPSEL is zero �� = �� + �� • �� + 1 • • • • where BTCTRL.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated. 22.6.3 Additional Features 22.6.3.1 Linked Descriptors A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of several block transfers it is done with the help of linked descriptors.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 7. Go to step 4 if needed. 22.6.3.1.3 Adding a Descriptor Between Existing Descriptors To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the DMA must be identified. 1. 2. If DMA is executing descriptor B, descriptor C cannot be inserted. If DMA has not started to execute descriptor A, follow the steps: 2.1. Set the descriptor A VALID bit to '0'. 2.2. 2.3. 2.4. 3.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be set. Note: Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be suspended, the internal suspend command will be ignored. For more details on transfer descriptors, refer to section 22.6.2.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels register (PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event trigger is lost. The figure below shows an example where beat transfers are enabled by internal events. Figure 22-12.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Conditional Transfer The event input is used to trigger a conditional transfer on peripherals with pending transfer requests. As example, this type of event can be used for peripheral-to-peripheral transfers, where one peripheral is the source of event and the second peripheral is the source of the trigger. Each peripheral trigger is stored internally when the event is received.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Channel Resume The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details refer to 22.6.3.3 Channel Suspend. Skip Next Block Suspend This event can be used to skip the next block suspend action.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Figure 22-17. Burst Event Output Generation Block Transfer Data Transfer Block Transfer BURST BURST BURST BURST Event Output Trigger action event output When the trigger action event output is selected, an event level is generated. Then event output is set when the transfer trigger occurred, and cleared when the corresponding trigger action is completed. The figure below shows an example for each trigger action type. Figure 22-18.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the channel is disabled. The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire DMAC module is disabled. 22.6.3.8 CRC Operation A Cyclic Redundancy Check (CRC) is an error detection technique used to find errors in data.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Figure 22-19. CRC Generator Block Diagram DMAC Channels CRCDATAIN CRCCTRL 8 16 8 CRC-16 32 CRC-32 crc32 CHECKSUM bit-reverse + complement Checksum read CRC on CRC-16 or CRC-32 calculations can be performed on data passing through any DMA DMA channel. Once a DMA channel is selected as the source, the CRC engine will continuously data generate the CRC on the data passing through the DMA channel.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller initial checksum value (CHKINIT) stored in the Block Transfer Destination Address register (DSTADDR). The DMA read and calculate the checksum over the data from the source address.When the checksum calculation is completed, the CRC value is stored in the CRC Checksum register (CRCCHKSUM), the Transfer Complete interrupt flag is set (CHINTFLAGn.TCMPL) and optional interrupt is generated.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.6.3.10 Memory CRC Monitor When enabled, it is possible to continuously check a a memory block data integrity by calculating and checking the CRC checksum. The expected CRC checksum value must be located in the last memory block location, as shown in the table below: CRCCTRL.CRCPOLY CRCCTRL.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller – In the first list descriptor, set the destination address with the initial checksum value (DSTADDR = CHKINIT) – Set the transfer source address (SRCADDR) – Set the block transfer count (BTCNT) – Set the memory CRC monitor operation mode (CRCCTRL.CRCMODE = CRCMON) – Enable optional interrupts Enable the corresponding DMA channel (CHCTRLAn.ENABLE) 4. Figure 22-21.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the Interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear Interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.6.8 Synchronization Not applicable. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.7 Register Summary Offset Name 0x00 CTRL 0x02 0x04 CRCCTRL CRCDATAIN Bit Pos.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset 0x2C Name PENDCH Bit Pos.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 0x5E CHINTFLAG1 7:0 0x5F CHSTATUS1 7:0 CRCERR 7:0 0x60 0x64 CHCTRLA2 TRIGACT[1:0] 31:24 THRESHOLD[1:0] 0x65 CHPRILVL2 7:0 0x66 CHEVCTRL2 7:0 TERR BUSY PEND ENABLE SWRST TRIGSRC[7:0] 23:16 7:0 TCMPL FERR RUNSTDBY 15:8 CHCTRLB2 SUSP BURSTLEN[3:0] CMD[1:0] PRILVL[1:0] EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x67 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x90 CHCTRLA5 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0x94 CHCTRLB5 7:0 CMD[1:0] 0x95 CHPRILVL5 7:0 PRILVL[1:0] 0x96 CHEVCTRL5 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x97 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0xC0 CHCTRLA8 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0xC4 CHCTRLB8 7:0 CMD[1:0] 0xC5 CHPRILVL8 7:0 PRILVL[1:0] 0xC6 CHEVCTRL8 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0xC7 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0xF0 CHCTRLA11 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0xF4 CHCTRLB11 7:0 CMD[1:0] 0xF5 CHPRILVL11 7:0 PRILVL[1:0] 0xF6 CHEVCTRL11 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0xF7 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x0120 CHCTRLA14 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0x0124 CHCTRLB14 7:0 CMD[1:0] 0x0125 CHPRILVL14 7:0 PRILVL[1:0] 0x0126 CHEVCTRL14 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x0127 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x0150 CHCTRLA17 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0x0154 CHCTRLB17 7:0 CMD[1:0] 0x0155 CHPRILVL17 7:0 PRILVL[1:0] 0x0156 CHEVCTRL17 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x0157 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x0180 CHCTRLA20 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0x0184 CHCTRLB20 7:0 CMD[1:0] 0x0185 CHPRILVL20 7:0 PRILVL[1:0] 0x0186 CHEVCTRL20 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x0187 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x01B0 CHCTRLA23 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0x01B4 CHCTRLB23 7:0 CMD[1:0] 0x01B5 CHPRILVL23 7:0 PRILVL[1:0] 0x01B6 CHEVCTRL23 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x01B7 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x01E0 CHCTRLA26 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0x01E4 CHCTRLB26 7:0 CMD[1:0] 0x01E5 CHPRILVL26 7:0 PRILVL[1:0] 0x01E6 CHEVCTRL26 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x01E7 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x0210 CHCTRLA29 RUNSTDBY ENABLE 15:8 SWRST TRIGSRC[7:0] 23:16 TRIGACT[1:0] 31:24 THRESHOLD[1:0] BURSTLEN[3:0] 0x0214 CHCTRLB29 7:0 CMD[1:0] 0x0215 CHPRILVL29 7:0 PRILVL[1:0] 0x0216 CHEVCTRL29 7:0 EVOE EVIE EVOMODE[1:0] EVACT[2:0] 0x0217 ...
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Value 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Name CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Description DMA channel 12 DMA channel 13 DMA channel 14 DMA channel 15 DMA channel 16 DMA channel 17 DMA channel 18 DMA channel 19 DMA channel 20 DMA channel 21 DMA channel 22 DMA channel 23 DMA channel 24 DMA channel 25 DMA chan
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.4 CRC Checksum Name: Offset: Reset: Property: CRCCHKSUM 0x08 0x00000000 PAC Write Protection, Enable-Protected The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write this register only when the CRC module is disabled.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.5 CRC Status Name: Offset: Reset: Property: Bit 7 CRCSTATUS 0x0C 0x00 PAC Write-Protection 6 5 4 3 2 1 0 CRCERR CRCZERO CRCBUSY Access R R R/W Reset 0 0 0 Bit 2 – CRCERR CRC Error This bit is read '1' when the memory CRC monitor detects data corruption. Bit 1 – CRCZERO CRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC Checksum is zero.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.6 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0D 0x00 PAC Write Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a Software Reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The DMAC is halted when the CPU is halted by an external debugger.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.9 Interrupt Pending Name: Offset: Reset: Property: INTPEND 0x20 0x0000 - This register allows the user to identify the lowest DMA channel with pending interrupt. An interrupt that handles several channels should consult the INTPEND register to find out which channel number has priority (ignoring/filtering each channel that has its own interrupt line). An interrupt dedicated to only one channel must not use the INTPEND register.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Bit 8 – TERR Transfer Error This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID).
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.16 Channel Control A Name: Offset: Reset: Property: Bit 31 CHCTRLA 0x40 + n*0x10 [n=0..
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Value 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Name 8BEAT 9BEAT 10BEAT 11BEAT 12BEAT 13BEAT 14BEAT 15BEAT 16BEAT Description 8-beats burst length 9-beats burst length 10-beats burst length 11-beats burst length 12-beats burst length 13-beats burst length 14-beats burst length 15-beats burst length 16-beats burst length Bits 21:20 – TRIGACT[1:0] Trigger Action These bits define the trigger action used for a transfer.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller ...........
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.17 Channel Control B Name: Offset: Reset: Property: Bit 7 CHCTRLB 0x44 + n*0x10 [n=0..31] 0x00 PAC Write-Protection 6 5 4 3 2 1 0 CMD[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – CMD[1:0] Software Command These bits define the software commands. Refer to 22.6.3.3 Channel Suspend and 22.6.3.4 Channel Resume and Next Suspend Skip. These bits are not enable-protected.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.18 Channel Priority Level Name: Offset: Reset: Property: Bit 7 CHPRILVL 0x45 + n*0x10 [n=0..31] 0x00 PAC Write-Protection 6 5 4 3 2 1 0 PRILVL[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – PRILVL[1:0] Channel Priority Level These bits define the priority level used for the DMA channel. The available levels are shown below, where a high level has priority over a low level. These bits are not enable-protected.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.19 Channel Event Control Name: Offset: Reset: Property: Bit Access Reset CHEVCTRL 0x46 + n*0x10 [n=0..31] 0x00 PAC Write-Protection, Enable-Protected 7 6 5 4 3 2 EVOE EVIE R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 EVOMODE[1:0] 1 0 EVACT[2:0] Bit 7 – EVOE Channel Event Output Enable This bit indicates if the Channel event generation is enabled.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.20 Channel Interrupt Enable Clear Name: Offset: Reset: Property: CHINTENCLR 0x4C + n*0x10 [n=0..31] 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.21 Channel Interrupt Enable Set Name: Offset: Reset: Property: CHINTENSET 0x4D + n*0x10 [n=0..31] 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.22 Channel Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 CHINTFLAG 0x4E + n*0x10 [n=0..31] 0x00 - 6 5 4 3 Access Reset 2 1 0 SUSP TCMPL TERR R/W R/W R/W 0 0 0 Bit 2 – SUSP Channel Suspend This flag is cleared by writing a '1' to it.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.8.23 Channel Status Name: Offset: Reset: Property: Bit 7 CHSTATUS 0x4F + n*0x10 [n=0..31] 0x00 - 6 Access Reset 5 4 3 2 1 0 CRCERR FERR BUSY PEND R/W R R R 0 0 0 0 Bit 3 – CRCERR Channel CRC Error This bit is set when the CRC monitor detects data corruption. This bit is cleared bu writing '1' to it, or by clearing the CRC Error bit in the INTPEND register (INTPEND.CRCERR).
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.9 Register Summary - SRAM Offset Name 0x00 BTCTRL 0x02 0x04 0x08 0x0C 22.10 BTCNT SRCADDR DSTADDR DESCADDR Bit Pos.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.10.1 Block Transfer Control Name: Offset: Property: BTCTRL 0x00 - The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 STEPSIZE[2:0] 12 11 10 9 STEPSEL DSTINC SRCINC 4 3 2 8 BEATSIZE[1:0] Access Reset Bit 7 6 5 BLOCKACT[1:0] 1 EVOSEL[1:0] 0 VALID Access Reset Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size These bits select the address increment step size.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Bit 10 – SRCINC Source Address Increment Enable Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller Value 1 Description The descriptor is valid © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.10.2 Block Transfer Count Name: Offset: Property: BTCNT 0x02 - The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 3 2 1 0 BTCNT[15:8] Access Reset Bit 7 6 5 4 BTCNT[7:0] Access Reset Bits 15:0 – BTCNT[15:0] Block Transfer Count This bit group holds the 16-bit block transfer count.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.10.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.10.
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SAM D5x/E5x Family Data Sheet DMAC – Direct Memory Access Controller 22.10.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23. EIC – External Interrupt Controller 23.1 Overview The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.4 Signal Description Signal Name Type Description EXTINT[15..0] Digital Input External interrupt pin NMI Digital Input Non-maskable interrupt pin One signal may be available on several pins. 23.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 23.5.1 I/O Lines Using the EIC’s I/O lines requires the I/O pins to be configured. Related Links 32.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.5.4 DMA Not applicable. 23.5.5 Interrupts There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for Non-Maskable Interrupt (NMI). The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller Related Links 23.6.3 External Pin Processing 23.6.2 Basic Operation 23.6.2.1 Initialization The EIC must be initialized in the following order: 1. 2. 3. Enable CLK_EIC_APB If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL) Enable GCLK_EIC or CLK_ULP32K when one of the following configuration is selected: – the NMI uses edge detection or filtering. – one EXTINT uses filtering.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.6.3 External Pin Processing Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the Config n register (CONFIG.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (23.8.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller Figure 23-2. Interrupt Detection Latency by modes (Rising Edge) GCLK_EIC CLK_EIC_APB EXTINTx intreq_extint[x] (level detection / no filter) No interrupt intreq_extint[x] (level detection / filter) intreq_extint[x] (edge detection / no filter) No interrupt intreq_extint[x] (edge detection / filter) clear INTFLAG.EXTINT[x] The detection latency depends on the detection mode. Table 23-2.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller In Synchronous Edge Detection Mode, the external interrupt (EXTINT) or the non-maskable interrupt (NMI) pins are sampled using the EIC clock as defined by the Clock Selection bit in the Control A register (CTRLA.CKSEL). The External Interrupt flag (INTFLAG.EXTINT[x]) or Non-Maskable Interrupt flag (NMIFLAG.NMI) is set when the last sampled state of the pin differs from the previously sampled state. In this mode, the EIC clock is required.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 4. 5. When the transition counter meets the count threshold, the pin edge transition is validated and the pin state PINSTATE.PINSTATE[x] is changed to the detected level. The external interrupt flag (INTFLAG.EXTINT[x]) is set when the pin state PINSTATE.PINSTATE[x] is changed. Figure 23-3.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller Each interrupt source has an associated Interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when an Interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1).
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.6.9 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written: • Software Reset bit in control register (CTRLA.SWRST) • Enable bit in control register (CTRLA.ENABLE) Required write synchronization is denoted by the "Write-Synchronized" property in the register description.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.7 Register Summary Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller ...........continued Offset Name Bit Pos. 7:0 0x34 DPRESCALER STATES1 PRESCALER1[2:0] STATES0 PRESCALER0[2:0] 15:8 23:16 TICKON 31:24 0x38 PINSTATE 7:0 PINSTATE[7:0] 15:8 PINSTATE[15:8] 23:16 31:24 23.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronized 6 Access Reset 5 4 3 2 1 0 CKSEL ENABLE SWRST RW RW W 0 0 0 Bit 4 – CKSEL Clock Selection The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32KHz is required for filtering) or by CLK_ULP32K (when power consumption is the priority). This bit is not Write-Synchronized.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.2 Non-Maskable Interrupt Control Name: Offset: Reset: Property: Bit 7 NMICTRL 0x01 0x00 PAC Write-Protection 6 Access Reset 5 4 3 2 1 0 NMIASYNCH NMIFILTEN R/W R/W R/W R/W R/W 0 0 0 0 0 NMISENSE[2:0] Bit 4 – NMIASYNCH Asynchronous Edge Detection Mode The NMI edge detection can be operated synchronously or asynchronously to the EIC clock. Value Description 0 The NMI edge detection is synchronously operated.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.3 Non-Maskable Interrupt Flag Status and Clear Name: Offset: Reset: Bit NMIFLAG 0x02 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit NMI Access RW Reset 0 Bit 0 – NMI Non-Maskable Interrupt This flag is cleared by writing a '1' to it. This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.4 Synchronization Busy Name: Offset: Reset: Bit SYNCBUSY 0x04 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Access Reset Bit Access Reset Bit Access Reset Bit 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.6 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x0C 0x00000000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.7 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x10 0x00000000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.10 External Interrupt Sense Configuration n Name: Offset: Reset: Property: Bit 31 CONFIG 0x1C + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller Value 0x4 0x5 0x6 0x7 Name F/32 F/64 F/128 F/256 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet EIC – External Interrupt Controller 23.8.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24. GMAC - Ethernet MAC The description and registers of this peripheral are using the 'GMAC' designation although the device does not support Gigabit Ethernet functionality. 24.1 Description The Ethernet Media Access Controller (GMAC) module implements a 10/100 Mbps Ethernet MAC, compatible with the IEEE 802.3 standard. The GMAC can operate in either half or full duplex mode at all supported speeds. 24.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.3 Block Diagram Figure 24-1. Block Diagram Status & Statistic Registers Register Interface APB MDIO Control Registers AHB DMA Interface AHB MAC Transmitter FIFO Interface Media Interface MAC Receiver Frame Filtering Packet Buffer Memories 24.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Signal Name Function MII RMII GMDC Management Data Clock MDC MDC GMDIO Management Data Input/Output MDIO MDIO • 24.5 Product Dependencies 24.5.1 I/O Lines Using the GMAC I/O lines requires the I/O pins to be configured using the port configuration (PORT). Related Links 6. I/O Multiplexing and Considerations 32. PORT - I/O Pin Controller 24.5.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 31. EVSYS – Event System 24.6 Functional Description 24.6.1 Media Access Controller The Transmit Block of the Media Access Controller (MAC) takes data from FIFO, adds preamble, checks and adds padding and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of operation are supported.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC • Support for Transmit TCP/IP checksum offload • Support for priority queuing • When a collision on the line occurs during transmission, the packet will be automatically replayed directly from the packet buffer memory rather than having to re-fetch through the AHB (full store and forward ONLY) • Received erroneous packets are automatically dropped before any of the packet is presented to the AHB (full store and forward ONLY), thus reducing AHB activity • Sup
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Table 24-2. Receive Buffer Descriptor Entry Bit Function Word 0 31:2 Address of beginning of buffer 1 Wrap—marks last descriptor in receive buffer descriptor list. 0 Ownership—needs to be zero for the GMAC to write data to the receive buffer. The GMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Bit Function 23:22 This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration) Type ID register match. Encoded as follows: 00: Type ID register 1 match 01: Type ID register 2 match 10: Type ID register 3 match 11: Type ID register 4 match If more than one Type ID is matched only one is indicated with priority 4 down to 1.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Bit Function 12:0 These bits represent the length of the received frame which may or may not include FCS depending on whether FCS discard mode is enabled. With FCS discard mode disabled: (bit 17 clear in Network Configuration Register) Least significant 12 bits for length of frame including FCS. If jumbo frames are enabled, these 12 bits are concatenated with bit[13] of the descriptor above.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC rare occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 Bytes for the receive buffers size. When in packet buffer full store and forward mode, only good received frames are written out of the DMA, so no fragments will exist in the AHB buffers due to MAC receiver errors. There is still the possibility of fragments due to DMA errors, for example used bit read on the second buffer of a multi-buffer frame.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC length of 64 Bytes. When CRC is not automatically generated (as defined in word 1 of the transmit buffer descriptor), the frame is assumed to be at least 64 Bytes long and pad is not generated. An entry in the transmit buffer descriptor list is described in this table: Table 24-3. Transmit Buffer Descriptor Entry Bit Function Word 0 31:0 Byte address of buffer Word 1 31 Used—must be zero for the GMAC to read data to the transmit buffer.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Bit Function 16 No CRC to be appended by MAC. When set, this implies that the data in the buffers already contains a valid CRC, hence no CRC or padding is to be appended to the current frame by the MAC. This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a frame.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC To set TXGO, write a '1' to NCR.TSTART. Transmit halt does not take effect until any ongoing transmit finishes. If the DMA is configured for packet buffer Partial Store and Forward mode and a collision occurs during transmission of a multi-buffer frame, transmission will automatically restart from the first buffer of the frame.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Figure 24-2. Data Paths with Packet Buffers Included TX GMII MAC Transmitter TX Packet Buffer DPSRAM TX Packet Buffer APB Register Interface TX DMA Status and Statistic Registers AHB AHB DMA RX DMA MDIO Control Interface RX Packet Buffer DPSRAM RX Packet Buffer RX GMII MAC Receiver Ethernet MAC Frame Filtering 24.6.3.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Note: If full store and forward mode is active and if a single frame is fetched that is too large for the packet buffer memory, the frame is flushed and the DMA halted with an error status. This is because a complete frame must be written into the packet buffer before transmission can begin, and therefore the minimum packet buffer memory size should be chosen to satisfy the maximum frame to be transmitted in the application.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC frame data has been transferred to the packet buffer, the status and statistics are updated to the GMAC registers. If Partial Store and Forward mode is active, the DMA will begin fetching the packet data before the status is available. As soon as the status becomes available, the DMA will fetch this information as soon as possible before continuing to fetch the remainder of the frame.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC By setting when bit 28 is set in the Network Configuration register, the Inter Packet Gap (IPG) may be stretched beyond 96 bits depending on the length of the previously transmitted frame and the value written to the IPG Stretch register (IPGS). The least significant 8 bits of the IPG Stretch register multiply the previous frame length (including preamble).
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in significant performance improvements.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC frame will still be transmitted but without the checksum substitution, as typically the reason that the substitution did not occur was that the protocol was not recognized. 24.6.7 MAC Filtering Block The filter block determines which frames should be written to the FIFO interface and on to the DMA.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC DA (Octet 4) A9 DA (Octet 5 - MSB) CB SA (LSB) 00 (see Note) SA 00(see Note) SA 00(see Note) SA 00(see Note) SA 00(see Note) SA (MSB) 00(see Note) Type ID (MSB) 43 Type ID (LSB) 21 Note: Contains the address of the transmitting device. The previous sequence shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom, as shown.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC If the hash index points to a bit that is set in the Hash register then the frame will be matched according to whether the frame is multicast or unicast. A multicast match will be signaled if the multicast hash enable bit is set, da[0] is logic 1 and the hash index points to a bit set in the Hash register. A unicast match will be signaled if the unicast hash enable bit is set, da[0] is logic 0 and the hash index points to a bit set in the Hash register.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC • Specific address 1 filter match • Multicast hash filter match These events can be individually enabled through bits [19:16] of the Wake on LAN register. Also, for Wake on LAN detection to occur, receive enable must be set in the Network Control register, however a receive buffer does not have to be available. In case of an ARP request, specific address 1 or multicast filter events will occur even if the frame is errored.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC IEEE 802.1AS is a subset of IEEE 1588. One difference is that IEEE 802.1AS uses the Ethernet multicast address 0180C200000E for sync frame recognition whereas IEEE 1588 does not. GMAC is designed to recognize sync frames with both IEEE 802.1AS and IEEE 1588 addresses and so can support both 1588 and 802.1AS frame recognition simultaneously. Synchronization between master and slave clocks is a two stage process.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Frame Segment Value Control (Octet 74) 01 Other stuff (Octets 75–168) — For 1588 version 1 messages, sync and delay request frames are indicated by the GMAC if the frame type field indicates TCP/IP, UDP protocol is indicated, the destination IP address is 224.0.1.129/130/131 or 132, the destination UDP port is 319 and the control field is correct. The control field is 0x00 for sync frames and 0x01 for delay request frames.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Frame Segment Value IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–33) E000006B Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–41) — Message type (Octet 42) 02 Version PTP (Octet 43) 02 Table 24-9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Frame Segment Value Version PTP (Octet 15) 02 24.6.15 Time Stamp Unit Overview The TSU consists of a timer and registers to capture the time at which PTP event frames cross the message timestamp point. An interrupt is issued when a capture register is updated. The 1588 time stamp unit (TSU) is implemented as a 94-bit timer.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC There are eight additional 80-bit registers that capture the time at which PTP event frames are transmitted and received. An interrupt is issued when these registers are updated. The TSU timer count value can be compared to a programmable comparison value. For the comparison, the 48 bits of the seconds value and the upper 22 bits of the nanoseconds value are used.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero (assuming it has been enabled by bit 13 in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received. 24.6.16.2 802.3 Pause Frame Transmission Automatic transmission of pause frames is supported through the transmit pause frame bits of the Network Control register.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC • As an architectural convenience in writing the 802.3az it is assumed that transmission is deferred by asserting carrier sense - in practice it will not be done this way. This system will know when it has nothing to transmit and only enter low power mode when it is not transmitting. • LPI should not be requested unless the link has been up for at least one second.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.6.20 10/100 Operation The 10/100 Mbps speed bit in the Network Configuration register is used to select between 10 Mbps and 100 Mbps. 24.6.21 Jumbo Frames The jumbo frames enable bit in the Network Configuration register allows the GMAC, in its default configuration, to receive jumbo frames up to 10240 bytes in size. This operation does not form part of the IEEE 802.3 specification and is normally disabled.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 3. 4. 5. Mark the last descriptor in the queue with the wrap bit (bit 1 in word 0 set to 1). Write address of receive buffer descriptor list and control information to GMAC register receive buffer queue pointer The receive circuits can then be enabled by writing to the address recognition registers and the Network Control register. 24.7.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC The Management Data Clock (MDC) should not toggle faster than 2.5 MHz (minimum period of 400 ns), as defined by the IEEE 802.3 standard. MDC is generated by dividing down MCK. Three bits in the Network Configuration register determine by how much MCK should be divided to produce MDC. 24.7.1.6 Interrupts There are 18 interrupt conditions that are detected within the GMAC. The conditions are ORed to make a single interrupt.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC receive buffer not available interrupt is set. If the frame is not successfully received, a statistics register is incremented and the frame is discarded without informing software. 24.7.2 Statistics Registers Statistics registers are described in the User Interface beginning with Section 1.8.48 ”GMAC Octets Transmitted Low Register” and ending with Section 1.8.92 ”GMAC UDP Checksum Errors Register”.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Once a statistics register has been read, it is automatically cleared. When reading the Octets Transmitted and Octets Received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.8 Offset 0x00 Register Summary Name NCR Bit Pos.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0x28 Name IER Bit Pos.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0x84 0x88 0x8C Name HRT SAB0 SAT0 Bit Pos.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0xB0 Name TIDM2 Bit Pos. 7:0 TID[7:0] 15:8 TID[15:8] 23:16 31:24 0xB4 TIDM3 7:0 TID[7:0] 15:8 TID[15:8] 23:16 31:24 0xB8 WOL ENIDn ENIDn 7:0 IP[7:0] 15:8 IP[15:8] 23:16 MTI SA1 ARP MAG 31:24 0xBC IPGS 7:0 FL[7:0] 15:8 FL[15:8] 23:16 31:24 0xC0 SVLAN 7:0 VLAN_TYPE[7:0] 15:8 VLAN_TYPE[15:8] 23:16 31:24 ESVLAN 0xC4 ...
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0xE4 Name SCH Bit Pos. 7:0 SEC[7:0] 15:8 SEC[15:8] 23:16 31:24 0xE8 EFTSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xEC EFRSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xF0 PEFTSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xF4 PEFRSH 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 31:24 0xF8 ...
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0x0114 Name PFT Bit Pos.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0x016C 0x0170 0x0174 0x0178 0x017C 0x0180 0x0184 Name TBFR127 TBFR255 TBFR511 TBFR1023 TBFR1518 TMXBFR UFR Bit Pos.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset Name Bit Pos. 7:0 0x0198 RSE RXSE[7:0] 15:8 RXSE[9:8] 23:16 31:24 7:0 0x019C AE AER[7:0] 15:8 AER[9:8] 23:16 31:24 0x01A0 RRE 7:0 RXRER[7:0] 15:8 RXRER[15:8] 23:16 RXRER[17:16] 31:24 7:0 0x01A4 ROE RXOVR[7:0] 15:8 RXOVR[9:8] 23:16 31:24 7:0 0x01A8 IHCE HCKER[7:0] 15:8 23:16 31:24 7:0 0x01AC TCE TCKER[7:0] 15:8 23:16 31:24 7:0 0x01B0 UCE UCKER[7:0] 15:8 23:16 31:24 0x01B4 ...
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0x01C8 0x01CC Name TSSSL TSSN Bit Pos.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC ...........continued Offset 0x01F4 Name PEFTN Bit Pos. 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 0x01F8 0x01FC PEFRSL PEFRN RUD[29:24] 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[31:24] 7:0 RUD[7:0] 15:8 RUD[15:8] 23:16 RUD[23:16] 31:24 RUD[29:24] 0x0200 ...
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Value 0 1 Description Normal operation All received frames' CRC is replaced with a time stamp Bit 12 – TXZQPF Transmit Zero Quantum Pause Frame Writing a '1' to this bit causes a pause frame with zero quantum to be transmitted. Writing a '0' to this bit has no effect. Bit 11 – TXPF Transmit Pause Frame Writing one to this bit causes a pause frame to be transmitted. Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit 3 – TXEN Transmit Enable Writing a '1' to this bit enables the GMAC transmitter to send data. Writing a '0' to this bit stops transmission immediately, the transmit pipeline and control registers is cleared, and the Transmit Queue Pointer Register will be set to point to the start of the transmit descriptor list.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit 24 – RXCOEN Receive Checksum Offload Enable Writing a '1' to this bit enables the receive checksum engine, and frames with bad IP, TCP or UDP checksums are discarded. Bit 23 – DCPF Disable Copy of Pause Frames Writing a '1' to this bit prevents valid pause frames from being copied to memory. Pause frames are not copied regardless of the state of the Copy All Frames (CAF) bit, whether a hash match is found or whether a type ID match is identified.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC When writing a '1' to this bit, the back-off between collisions will always be one slot time. This setting helps testing the too many retries condition. This setting is also useful for pause frame tests by reducing the pause counter's decrement time from "512 bit times" to "every GRXCK cycle". Bit 8 – MAXFS 1536 Maximum Frame Size Writing a '1' to this bit increases the maximum accepted frame size to 1536 bytes in length.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.3 GMAC Network Status Register Name: Offset: Reset: Property: Bit NSR 0x008 0x00000004 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 Access Reset Bit Access Reset Bit Access Reset Bit 2 1 IDLE MDIO Access R R Reset 1 0 Bit 2 – IDLE PHY Management Logic Idle The PHY management logic is idle (i.e., has completed).
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.4 GMAC User Register Name: Offset: Reset: Property: Bit UR 0x00C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 MII Access R/W Reset 0 Bit 0 – MII Value 0 1 Reduced MII Mode Description RMII mode is selected MII mode is selected © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Value Description 0x00 Reserved 0x01-0x 1..255 x 64 byte buffer FF Bit 11 – TXCOEN Transmitter Checksum Generation Offload Enable Transmitter IP, TCP and UDP checksum generation offload enable. Value Description 0 Frame data is unaffected. 1 The transmitter checksum generation engine calculates and substitutes checksums for transmit frames.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Value 2 4 8 16 Name INCR4 INCR8 INCR16 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.6 GMAC Transmit Status Register Name: Offset: Reset: Property: Bit TSR 0x014 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Access Reset Bit Access Reset Bit 8 HRESP Access R/W Reset Bit Access Reset 0 7 6 5 4 3 2 1 0 UND TXCOMP TFC TXGO RLE COL UBR R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bit 8 – HRESP HRESP Not OK Set when the DMA block sees HRESP not OK.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC In DMA packet buffer mode, this bit is also set if a single frame is too large for the configured packet buffer memory size. This bit is cleared by writing a '1' to it. Bit 3 – TXGO Transmit Go This bit is '1' when transmit is active. When using the DMA interface this bit represents the TXGO variable as specified in the transmit buffer description. Bit 2 – RLE Retry Limit Exceeded This bit is cleared by writing a '1' to it.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.7 GMAC Receive Buffer Queue Base Address Register Name: Offset: Reset: Property: RBQB 0x018 0x00000000 Read/Write This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the Network Control Register. Once reception is enabled, any write to the Receive Buffer Queue Base Address Register is ignored.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.8 GMAC Transmit Buffer Queue Base Address Register Name: Offset: Reset: Property: TBQB 0x01C 0x00000000 - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.9 GMAC Receive Status Register Name: Offset: Reset: Property: RSR 0x020 0x00000000 - This register, when read, provides receive status details. Once read, individual bits may be cleared by writing a '1' to them. It is not possible to set a bit to '1' by writing to this register.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.10 GMAC Interrupt Status Register Name: Offset: Reset: Property: ISR 0x024 0x00000000 - This register indicates the source of the interrupt. An interrupt source must be enabled in the mask register first so the corresponding bits of this register will be set and the GMAC interrupt signal will be asserted in the system.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit 23 – PDRSFR PDelay Response Frame Received Indicates a PTP pdelay_resp frame has been received. Cleared on read. Bit 22 – PDRQFR PDelay Request Frame Received Indicates a PTP pdelay_req frame has been received. Cleared on read. Bit 21 – SFT PTP Sync Frame Transmitted Indicates a PTP sync frame has been transmitted. Cleared on read. Bit 20 – DRQFT PTP Delay Request Frame Transmitted Indicates a PTP delay_req frame has been transmitted. Cleared on read.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit 6 – TFC Transmit Frame Corruption Due to AHB Error Transmit frame corruption due to AHB error. Set if an error occurs during reading a transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame. Bit 5 – RLEX Retry Limit Exceeded Retry Limit Exceeded Transmit error. Cleared on read.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.11 GMAC Interrupt Enable Register Name: Offset: Reset: Property: IER 0x028 – Write-only This register is write-only and will always return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit 19 – SFR PTP Sync Frame Received Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Time Zero Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Bit 11 – HRESP HRESP Not OK Bit 10 – ROVR Receive Overrun Bit 7 – TCOMP Transmit Complete Bit 6 – TFC Transmit Frame Corruption Due to AHB Error Bit 5 – RLEX Retry Limit Exceeded or Late Collision Bit 4 – TUR Tran
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.12 GMAC Interrupt Disable Register Name: Offset: Reset: Property: IDR 0x02C – Write-only This register is write-only and will always return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit 21 – SFT PTP Sync Frame Transmitted Bit 20 – DRQFT PTP Delay Request Frame Transmitted Bit 19 – SFR PTP Sync Frame Received Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Time Zero Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Bit 11 – HRESP HRESP Not OK Bit 10 – ROVR Receive Overrun Bit 7 – TCOMP Transmit Complete Bit 6 – TFC Transmit Frame Corru
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.13 GMAC Interrupt Mask Register Name: Offset: Reset: Property: IMR 0x030 0x07FFFFFF - This register is a read-only register indicating which interrupts are masked. All bits are set at Reset and can be reset individually by writing to the Interrupt Enable Register (IER), or set individually by writing to the Interrupt Disable Register (IDR).
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit 25 – PDRSFT PDelay Response Frame Transmitted Bit 24 – PDRQFT PDelay Request Frame Transmitted Bit 23 – PDRSFR PDelay Response Frame Received Bit 22 – PDRQFR PDelay Request Frame Received Bit 21 – SFT PTP Sync Frame Transmitted Bit 20 – DRQFT PTP Delay Request Frame Transmitted Bit 19 – SFR PTP Sync Frame Received Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Tim
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.14 GMAC PHY Maintenance Register Name: Offset: Reset: Property: MAN 0x034 0x00000000 Read/Write This register is a shift register. Writing to it starts a shift operation which is signaled completed when bit 2 is set in the Network Status Register (NSR). It takes about 2000 MCK cycles to complete, when MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bit Access Reset Bit 31 30 WZO CLTTO 29 28 R/W R/W R/W R/W R/W 0 0 0 0 0 23 22 21 20 19 PHYA[0:0] Access 27 26 25 24 R/W R/W R/W 0 0 0 18 17 OP[1:0] PHYA[4:1] REGA[4:0] 16 WTN[1:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[15:8] Access DATA[7:0] Access
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bits 15:0 – DATA[15:0] PHY Data For a write operation, this field is written with the data to be written to the PHY. After a read operation, this field contains the data read from the PHY. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.20 GMAC Hash Register Bottom Name: Offset: Reset: Property: HRB 0x080 0x00000000 Read/Write The unicast hash enable (UNIHEN) and the multicast hash enable (MITIHEN) bits in the Network Configuration Register (NCFGR) enable the reception of hash matched frames.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.21 GMAC Hash Register Top Name: Offset: Reset: Property: HRT 0x084 0x00000000 Read/Write The Unicast Hash Enable (UNIHEN) and the Multicast Hash Enable (MITIHEN) bits in the Network Configuration Register (NCFGR) enable the reception of hash matched frames.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.22 GMAC Specific Address n Bottom Register Name: Offset: Reset: Property: SAB 0x88 + n*0x08 [n=0..3] 0x00000000 - The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.23 GMAC Specific Address n Top Register Name: Offset: Reset: Property: SAT 0x8C + n*0x08 [n=0..3] 0x00000000 - The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.24 GMAC Type ID Match n Register Name: Offset: Reset: Property: Bit 31 TIDM 0xA8 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC Bits 15:0 – IP[15:0] ARP Request IP Address Wake on LAN ARP request IP address. Written to define the 16 least significant bits of the target IP address that is matched to generate a Wake on LAN event. Value Description 0x0000 No Event generated, even if matched by the received frame. 0x0001- Wake on LAN Event generated for matching LSB of the target IP address. 0xFFFF © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.37 GMAC Octets Transmitted Low Register Name: Offset: Reset: Property: OTLO 0x100 0x00000000 Read-Only When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.38 GMAC Octets Transmitted High Register Name: Offset: Reset: Property: OTHI 0x104 0x00000000 Read-Only When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.57 GMAC Octets Received Low Register Name: Offset: Reset: Property: ORLO 0x150 0x00000000 Read-Only When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.58 GMAC Octets Received High Register Name: Offset: Reset: Property: ORHI 0x154 0x00000000 Read-only When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet GMAC - Ethernet MAC 24.9.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25. 25.1 NVMCTRL – Nonvolatile Memory Controller Overview Non-volatile memory (NVM) is a reprogrammable flash memory that retains program and data storage, even when powered off. The NVM Controller (NVMCTRL) embeds two banks; one bank can be read while the other is programmed (RWW). It is connected to the AHB and APB bus interfaces for system access to the NVM block.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.3 Block Diagram Figure 25-1. Block Diagram NVMCTRL NVM Block AHB0 Cache line 0 AHB2 Cache line 1 SmartEEPROM APB 25.4 AHBMUX AHB1 PAGE BUFFER BANKA NVM Interface Command and Control BANKB Signal Description Not applicable. 25.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described in the following sections. 25.5.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller proper number of wait states. Refer to the Electrical Characteristics for the exact number of wait states to be used for a particular frequency range. Automatic wait state generation can be use by setting the Auto Wait State bit in the Control A register (NVMCTRL.CTRLA.AUTOWS). Alternatively a custom programmable number of wait states can be set by writing the NVM Read Wait State bits (NVMCTRL.CTRLA.RWS) to optimize performance.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.6 Functional Description 25.6.1 Principle of Operation The NVM Controller is a slave on the AHB (AHB0, AHB1 and AHB2) and APB buses. It responds to commands, read requests and write requests, based on user configuration. AHB0 and AHB1 allow access to the NVM main address space, the auxiliarry space and the page buffer.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller The lower blocks in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT fuses, and the upper rows can be allocated to EEPROM. The NVM memory is separated into six parts: 1. 2. 3. 4. 5. 6. CB space Contains factory calibration and system configuration information. – Address; 0x00800000 – Size: 1 page – Property: Read-Only FS space Contains the factory signature information.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller hardfault exception. Any command issued with ADDR pointing in the SmartEEPPROM space is discarded, INTFLAG.DONE and INTFLAG.ADDRE are set in this case. – Address: PARAM.NVMP*512-2*SEESTAT.SBLK*8192 – Size: 2*SEESTAT.SBLK*8192 – Property: Not readable, not writeable Each section has different protection status, refer to the table below. Table 25-3.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Related Links 10.3 High-Speed Bus System 25.6.5 Region Lock Bits The NVM main address space is accessible through the AHB0 or AHB1 interfaces, and grouped into 32 equally sized regions regardless of BOOTPROT or SmartEEPROM settings. The region size is dependent on the flash memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller The APB ADDR register is updated upon: • APB writes to the ADDR register address • AHB writes to the page buffer ADDR APB writes are discarded and report an INTFLAG.ADDRE error in the following cases: • When written from APB while a command is reading it.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller ...........continued WP User Page Address Space WQW EP X X EB Issuing an unsupported command on an address space sets the PROGE interrupt flag. After programming the NVM main array, the region that the page resides in can be locked to prevent spurious write or erase sequences. Locking is performed on a per-region basis, and so locking a region locks all pages inside the region.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller – PBLDATA[63:0] = 0x00000003_0xFFFFFFFF BANKA and BANKB share the same page buffer. Writing to the NVM block via the AHB bus is buffered in the page buffer. For each AHB bus write, the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be written to the addressed location by setting CMD to Write Page to write the NVM main array and setting the key value to CMDEX.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller The block to be written must be erased before the last write to the page buffer is performed. The internal write operation will begin when the second word is written for WMODE = ADW, when the fourth word is written for WMODE = AQW, and when the last word of the page is written for WMODE = APW. Note that partially written pages must be written with a manual write.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller If a read occurs while executing one of the command listed above, the NVMCTRL will follow the following steps: 1. 2. 3. 4. Send a suspend command to the NVM. Wait for the NVM to be ready. Read the NVM. The NVMCTRL will persist in this step when a new read request occurs, or else proceed. Resume the suspended operation. A suspend operation will set INTFLAG.SUSP. To clear it write a ‘1’ to INTFLAG.SUSP.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.6.6.8 Power Reduction Mode The NVM implements a power reduction mode which cuts its static power consumption. If a command or a AHB access is issued the NVM is woken-up. The AHB access or the command are processed after the NVM wake-up time. The wake-up time can be reduced by enabling the PM fast wake-up feature, this is configured through the PM STDBYCFG register. The NVM Power Reduction Mode is entered depending on the CTRLA.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.6.7 Safe Flash Update Using Dual Banks This feature enables a firmware to execute from the NVM and at the same time program the Flash with a new version of itself. The new firmware has to be programmed in BANKB if STATUS.AFIRST=1, or BANKA otherwise. After programming is completed one can issue the BKSWRST command to swap the banks and to reset the device.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller • DATA – Starts at offset 0x0 – Size is 512B, 1KB, 2KB, 4KB, 8KB, 16KB, 32KB, 64KB depending on SEESTAT.PSZ and SEESTAT.SBLK (refer to “SmartEEPROM virtual size”) – This area is write protected if SEESTAT.LOCK is set. SEESTAT.LOCK is non volatile. – Commands LSEE and USEE respectively lock and unlock the SmartEEPROM. • REGISTER: – Starts at offset 0x10000 – Size is 20B – This area is write protected if either • SEESTAT.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Table 25-6. SmartEEPROM Virtual Size in Bytes SEESTAT.PSZ: SEESTAT.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller on the SEESTAT.PSZ and SEESTAT.SBLK user configuration. As there are two SEES the wear leveling is two times the maximum SEEP number. Table 25-8. Wear leveling depending on SEESTAT.PSZ and SEESTAT.SBLK SEESTAT 4 .PSZ: SEESTAT .
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller • BUFFERED: WP command triggered only in case of NVM page crossing. This mode increases the NVM wear-leveling but is more sensitive to power loss. SEESTAT.LOAD is high when the pagebuffer contains unwritten data. When SEECFG.WMODE selects the buffered mode, the page buffer can contain unwritten SmartEEPROM data. This is reflected by SEESTAT.LOAD. To flush the SmartEEPROM data inside the page buffer, issue the SEEFLUSH command. INTFLAG.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller ...........continued 25.6.9 SEESTAT 4 .PSZ: SEESTAT .SBLK 8 16 32 64 128 256 512 5 16 16 16 16 16 16 16 11 6 16 16 16 16 16 16 16 27 7 16 16 16 16 16 16 16 43 8 16 16 16 16 16 16 16 59 9 16 16 16 16 16 16 16 11 10 16 16 16 16 16 16 16 16 NVM User Configuration The NVM user configuration resides in the auxiliary space.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller ...........continued BOOTPROT [3:0] Rows Protected by BOOTPROT Boot Loader Size in KBytes 4 11 88 3 12 96 2 13 104 1 14 112 0 15 120 Table 25-11. SmartEEPROM Allocated Space SBLK[4:0] Total Blocks Bytes 10 20 163840 9 18 147456 8 16 131072 7 14 114688 6 12 98304 5 10 81920 4 8 65536 3 6 49152 2 4 32768 1 2 16384 0 0 0 Table 25-12.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.6.10 Security Bit The security bit allows the entire chip to be locked from external access for code security. Related Links 12. DSU - Device Service Unit 25.6.10.1 Security Bit Set Procedure 1. 2. 3. Issue the Set Security Bit command (SSB) This command changes the NVM security bits. The device shadow registers are not changed at that point.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.6.12.1 Block Diagram Figure 25-2. ECC Diagram PBLDATA[63:0] ECC calculation 8 64 HADDR ECCERR.ADDR NVM Block 144 64 64 8 ECC logic 8 ECC logic INTFLAG.ECCERR ECCERR.TYPEH 64 INTFLAG.ECCERR ECCERR.TYPEL 64 MATRIX 128 CACHE LINE AHB0 32 128 CACHE LINE AHB1 SmartEEPROM 32 Note that the ECC correction is disabled when access is performed by the SmartEEPROM interface. 25.6.12.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller ECCERR.TYPEL and ECCERR.TYPEH are reset to the NONE value when ECCERR is read. If an error occurs while reading ECCERR, the previous error information is sent to the APB and ECCERR is updated with the next error information. If a single-error has been detected and INTFLAG.ECCSE or INTFLAG.ECCDE is not clear: • Any incoming single-errors is ignored • First incoming dual-error overrides ECCERR.ADDR, ECCERR.TYPEL and ECCERR.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.7 Register Summary Offset Name 0x00 CTRLA Bit Pos. 7:0 PRM[1:0] 15:8 CACHEDIS1 CACHEDIS0 WMODE[1:0] AHBNS1 SUSPEN AHBNS0 AUTOWS RWS[3:0] 0x02 ... Reserved 0x03 0x04 CTRLB 7:0 CMD[6:0] 15:8 CMDEX[7:0] 0x06 ...
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller ...........continued Offset Name 0x29 Reserved 0x2A SEECFG 0x2B Reserved Bit Pos. 7:0 7:0 0x2C SEESTAT RLOCK 15:8 LOCK BUSY APRDIS WMODE LOAD ASEES SBLK[3:0] 23:16 PSZ[2:0] 31:24 25.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Bits 7:6 – PRM[1:0] Power Reduction Mode during Sleep Indicates the power reduction mode during sleep. Value Name Description 0x0 SEMIAUTO NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits lowpower mode upon first access. 0x1 FULLAUTO NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Value 0x12 Name UR 0x13 0x14 0x15 0x16 0x17 SPRM CPRM PBC SSB BKSWRST 0x18 0x19 0x1A CELCK CEULCK SBPDIS 0x1B 0x1C-0x 2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38-0x 7F CBPDIS ASEES0 ASEES1 SEERALOC SEEFLUSH LSEE USEE LSEER USEER Description Unlock Region - Unlocks the region containing the address location in the ADDR register until next reset. Sets the power reduction mode. Clears the power reduction mode.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.3 NVM Parameter Name: Offset: Property: Bit 31 PARAM 0x08 - 30 29 28 27 26 25 24 22 21 20 19 18 17 16 SEE Access R Reset Bit 23 PSZ[2:0] Access R R R 11 10 9 8 R R R R 3 2 1 0 R R R R Reset Bit 15 14 13 12 NVMP[15:8] Access R R R R 7 6 5 4 Reset Bit NVMP[7:0] Access R R R R Reset Bit 31 – SEE SmartEEPROM Supported 0: No SmartEEPROM support 1: SmartEEPROM is supported.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Writing a '1' to this bit clears the ECCSE interrupt enable. This bit will read as the current value of the ECCSE interrupt enable. Bit 3 – LOCKE Lock Error Interrupt Clear Writing a zero to this bit has no effect. Writing a '1' to this bit clears the LOCKE interrupt enable. This bit will read as the current value of the LOCKE interrupt enable. Bit 2 – PROGE Programming Error Interrupt Clear Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Writing a one to this bit sets the ECCSE interrupt enable. This bit will read as the current value of the ECCSE interrupt enable. Bit 3 – LOCKE Lock Error Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit sets the LOCKE interrupt enable. This bit will read as the current value of the LOCKE interrupt enable. Bit 2 – PROGE Programming Error Interrupt Enable Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 15 INTFLAG 0x10 0x0000 - 14 13 12 11 10 9 8 SEEWRC SEESOVF SEESFULL R/W R/W R/W 0 0 0 Access Reset Bit Access Reset 7 6 5 4 3 2 1 0 SUSP NVME ECCDE ECCSE LOCKE PROGE ADDRE DONE R/W R/W R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 10 – SEEWRC SEE Write Completed • Unbuffered mode: 0: AHB write is pending.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Bit 5 – ECCDE ECC Dual Error 0: No ECC dual errors have been received since the last ECCERR register read. 1: At least one ECC error has occurred since the last ECCERR register read. This bit is cleared when the ECCERR register is read. Bit 4 – ECCSE ECC Single Error 0: No ECC single errors have been received since the last ECCERR register read. 1: At least one ECC error has occurred since the last ECCERR register read.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.7 Status Name: Offset: Reset: Property: Bit 15 STATUS 0x12 0x0000 Read-Only 14 13 12 11 10 9 8 Access R R R R Reset 0 0 0 x BOOTPROT[3:0] Bit 7 6 5 4 3 2 1 0 BPDIS AFIRST SUSP LOAD PRM READY Access R R R R R R Reset 0 0 0 0 0 0 Bits 11:8 – BOOTPROT[3:0] Boot Loader Protection Size This bitfield is loaded from the USER page during the device startup.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Bit 0 – READY Ready to accept a command 0: The NVM controller is busy programming or erasing. 1: The NVM controller is ready to accept a new command. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.10 Page Buffer Load Data x Name: Offset: Reset: Property: PBLDATAn 0x1C + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.11 ECC Error Status Name: Offset: Reset: Property: ECCERR 0x24 0x00000000 - This register tracks errors on the NVM read path. ECC error tracking is active until an error is detected. It is still active in case of single error but no dual error. In this case only a dual error can override this register status as a dual error is more critical than a single error. Error tracking resumes as soon as this register is read.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Bits 23:0 – ADDR[23:0] Error Address Indicates the Byte address of the last detected error. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.12 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x28 0x00 PAC Write-Protection 6 5 4 3 2 1 0 ECCELOG ECCDIS R/W R/W 0 0 Access Reset Bit 1 – ECCELOG Debugger ECC Error Tracking Mode 0: ECC errors detected during a read initiated by a debugger are not logged. 1: ECC errors detected during a read initiated by a debugger are logged.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.13 SmartEEPROM Configuration Name: Offset: Reset: Property: Bit 7 SEECFG 0x2A 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 APRDIS WMODE R/W R/W 0 0 Bit 1 – APRDIS Automatic Page Reallocation Disable 0: enables the Automatic page Reallocation. 1: disables the Automatic page Reallocation. Bit 0 – WMODE Write Mode Indicates the type of bufferization used.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller 25.8.
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SAM D5x/E5x Family Data Sheet NVMCTRL – Nonvolatile Memory Controller Bit 1 – LOAD Page Buffer Loaded 0: SmartEEPROM has not left unwritten data in the page buffer. 1: SmartEEPROM has left unwritten data in the page buffer. Bit 0 – ASEES Active SmartEEPROM Sector This bit field is automatically loaded during startup from a special fuse in the NVM. Indicates the active SEES 0: SEES0 is active 1: SEES1 is active © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26. ICM - Integrity Check Monitor 26.1 Overview The Integrity Check Monitor (ICM) is a DMA controller that performs hash calculation over multiple memory regions through the use of transfer descriptors located in memory (ICM Descriptor Area). The Hash function is based on the Secure Hash Algorithm (SHA). The ICM controller integrates two modes of operation.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.3 Block Diagram Figure 26-1. Integrity Check Monitor Block Diagram APB Host Interface Configuration Registers SHA Hash Engine Context Registers Monitoring FSM Integrity Scheduler Master DMA Interface Bus Layer 26.4 Signal Description Not applicable. 26.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 26.5.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.5.3 DMA Not applicable. 26.5.4 Interrupts The ICM has an interrupt line connected to the Interrupt Controller. Handling the ICM interrupt requires programming the interrupt controller before configuring the ICM. Related Links 10.2 Nested Vector Interrupt Controller 26.5.5 Events Not applicable. 26.5.6 Debug Operation Not applicable. 26.6 Functional Description 26.6.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Figure 26-2.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.6.2 ICM Hash Area The ICM Hash Area is a contiguous area of system memory that the controller and the processor can access. The physical location is configured in the ICM hash area start address register. This address is a multiple of 128 bytes. If the CDWBN bit of the context register is cleared (i.e.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Memory Address Address Offset / Byte Lane 0x3 / 31:24 0x2 / 23:16 0x1 / 15:8 0x0 / 7:0 0x000 bf 16 78 ba 0x004 ea cf 01 8f 0x008 de 40 41 41 0x00C 23 22 ae 5d 0x010 a3 61 03 b0 0x014 9c 7a 17 96 0x018 61 ff 10 b4 0x01C ad 15 00 f2 Considering the following 1024 bits message (example given in FIPS 180-4): “6162638000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Example 26-1. ICM Monitoring of 3 Memory Data Blocks (Defined as 2 Regions) The following figure shows the mandatory ICM settings to monitor three memory data blocks of the system memory (defined as two regions) with one region being not contiguous (two separate areas) and one contiguous memory area. For each said region, the SHA algorithm may be independently selected (different for each region). The wrap allows continuous monitoring. Figure 26-4.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.6.3.1 Region Descriptor Structure Overview Offset 0x00 Name RADDR0 Bit Pos.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor ...........continued Offset 0x24 Name RADDR3 Bit Pos. 7:0 RADDR[7:0] 15:8 RADDR[15:8] 23:16 RADDR[23:16] 31:24 RADDR[31:24] 7:0 0x24 RNEXT2 15:8 23:16 31:24 7:0 0x28 RCFG3 WCIEN 15:8 BEIEN DMIEN RHIEN ALGO[2:0] EOM WRAP CDWBN PROCDLY SUIEN ECIEN 23:16 31:24 0x2C RCTRL3 7:0 TRSIZE[7:0] 15:8 TRSIZE[15:8] 23:16 31:24 7:0 0x30 RNEXT3 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.6.3.1.1 Region Start Address Structure Member Name: Offset: Reset: Property: Bit 31 RADDR 0x00 + n*0x0C [n=0..
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.6.3.1.2 Region Configuration Structure Member Name: Offset: Reset: Property: Bit RCFG 0x04 + n*0x0C [n=0..
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Bit 9 – SUIEN Monitoring Status Updated Condition Interrupt Enable 0: The RSU flag is set when the corresponding descriptor is loaded from memory to ICM. 1: The RSU flag remains cleared even if the condition is met. Bit 8 – ECIEN End Bit Condition Interrupt Enable 0: The REC flag is set when the descriptor having the EOM bit set is processed. 1: The REC flag remains cleared even if the setting condition is met.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.6.3.1.3 Region Control Structure Member Name: Offset: Reset: Property: Bit RCTRL 0x08 + n*0x0C [n=0..
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.6.3.1.4 Region Next Address Structure Member Name: Offset: Reset: Property: Bit RNEXT 0x0C + n*0x0C [n=0..3] 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 26.6.4 Using ICM as an SHA Engine The ICM can be configured to only calculate a SHA1, SHA224, SHA256 digest value. 26.6.4.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor • The flag REC[i], i being the region index, is set (if ECIEN is ‘0’) when the hash result is available at the address defined in HASH. An interrupt is generated if the bit RHC[i] is written to ‘1’ in the IER (if RHC[i] is set in RCTRL of region i) or if the bit REC[i] is written to 1 in the IER (if REC[i] is set in RCTRL of region i). 26.6.4.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.6.6 ICM Configuration Parameters Transfer Type Single Region Contiguous list of blocks Main List RCFG RNEXT CDWBN WRAP EOM NEXT 1 item 0 0 1 0 The Main List contains only one descriptor. The Secondary List is empty for that descriptor. The digest is computed and saved to memory. 1 item 0 0 1 Secondary List address of the current region identifier The Main List contains only one descriptor.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor ...........continued Transfer Type Multiple Regions Main List RCFG RNEXT CDWBN WRAP EOM NEXT Comments Contiguous list of blocks Digest written to memory Monitoring disabled More than one item 0 0 1 for the last, 0 otherwise 0 ICM passes through the list once. Contiguous list of blocks More than one item 1 1 for the last, 0 otherwise 0 0 ICM performs active monitoring of the regions.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.7 Offset Register Summary - ICM Name Bit Pos. 7:0 0x00 CFG 15:8 BBC[3:0] UALGO[2:0] SLBDIS UIHASH EOMDIS WBDIS DUALBUFF ASCD DISABLE ENABLE 23:16 31:24 0x04 CTRL 7:0 REHASH[3:0] 15:8 RMEN[3:0] SWRST RMDIS[3:0] 23:16 31:24 7:0 0x08 SR ENABLE 15:8 RMDIS[3:0] RAWRMDIS[3:0] 23:16 31:24 0x0C ...
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor ...........continued Offset Name Bit Pos. 7:0 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 26.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Related Links 26.6.3 Region Descriptor Structure © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Value 0 1 Description Automatic mode is disabled. When this mode is enabled, the ICM controller automatically switches to active monitoring after the first Main List pass. Both CDWBN and WBDIS bits have no effect. A '1' must be written to the End of Monitoring bit in the Region Configuration register (RCFG.EOM) to terminate the monitoring. Bits 7:4 – BBC[3:0] Bus Burden Control This field is used to control the burden of the ICM system bus.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.2 Control Register Name: Offset: Property: Bit CTRL 0x04 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 15 14 13 12 11 10 9 8 Access W W W W W W W W 7 6 5 4 3 Access Reset Bit Access Reset RMEN[3:0] RMDIS[3:0] Reset Bit REHASH[3:0] Access W W W W Reset 2 1 0 SWRST DISABLE ENABLE W W W 0 0 Bits 15:12 – RMEN[3:0] Region Monitoring Enable Value Description 0 No effect.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Value 0 1 Description No effect. The ICM controller is disabled. If a region is activated, the region is terminated. Bit 0 – ENABLE ICM Enable Value Description 0 No effect. 1 The ICM controller is activated. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Value 0 1 Description No effect. When RDM[i] is written to '1', the Region i Digest Mismatch interrupt is enabled. Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Enable Value Description 0 No effect. 1 When RHC[i] is written to '1', the Region i Hash Completed interrupt is enabled. © 2019 Microchip Technology Inc.
PAGE 713
SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Value 0 1 Description No effect. When RBE[i] is written to '1', the Region i Bus Error interrupt is disabled. Bits 7:4 – RDM[3:0] Region Digest Mismatch Interrupt Disable Value Description 0 No effect. 1 When RDM[i] is written to '1', the Region i Digest Mismatch interrupt is disabled. Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Disable Value Description 0 No effect.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Value 0 1 Description When RBE[i] is reading '0', the interrupt is disabled for region i. When RBE[i] is reading '1', the interrupt is enabled for region i. Bits 7:4 – RDM[3:0] Region Digest Mismatch Interrupt Mask Value Description 0 When RDM[i] is reading '0', the interrupt is disabled for region i. 1 When RDM[i] is reading '1', the interrupt is enabled for region i.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Bits 7:4 – RDM[3:0] Region Digest Mismatch RDM[i] is set when there is a digest comparison mismatch between the hash value of region i and the reference value located in the Hash Area. Bits 3:0 – RHC[3:0] Region Hash Completed RHC[i] is set when the ICM has completed the region with identifier i. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.8 Undefined Access Status Register Name: Offset: Reset: Property: Bit UASR 0x20 0x0 Read-Only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit URAT[2:0] Access R R R Reset 0 0 0 Bits 2:0 – URAT[2:0] Undefined Register Access Trace Only the first Undefined Register Access Trace is available through the URAT field.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor 26.8.11 User Initial Hash Value Register Name: Offset: Reset: Property: Bit UIHVALx 0x38 + x*0x04 [x=0..
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor Example Comment 0x98BADCFE SHA1 algorithm 0x3070DD17 SHA224 algorithm 0x3C6EF372 SHA256 algorithm For UIHVAL3 field: Example Comment 0x10325476 SHA1 algorithm 0xF70E5939 SHA224 algorithm 0xA54FF53A SHA256 algorithm For UIHVAL4 field: Example Comment 0xC3D2E1F0 SHA1 algorithm 0xFFC00B31 SHA224 algorithm 0x510E527F SHA256 algorithm For UIHVAL5 field: Example Comment 0x68581511 SHA224 algorithm 0x9B05688C SHA256 algorithm
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SAM D5x/E5x Family Data Sheet ICM - Integrity Check Monitor ...........continued Register Address Address Offset / Byte Lane 0x3 / 31:24 0x2 / 23:16 0x1 / 15:8 0x0 / 7:0 0x004 UIHVAL1 89 ab cd ef 0x008 UIHVAL2 fe dc ba 98 0x00C UIHVAL3 76 54 32 10 0x010 UIHVAL4 f0 e1 d2 c3 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27. PAC - Peripheral Access Controller 27.1 Overview The Peripheral Access Controller provides an interface for the locking and unlocking of peripheral registers within the device. It reports all violations that could happen when accessing a peripheral: write protected access, illegal access, enable protected access, access when clock synchronization or software reset is on-going.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Related Links 18. PM – Power Manager 27.4.3 Clocks The PAC bus clock (CLK_PAC_APB) can be enabled and disabled in the Main Clock module. The default state of CLK_PAC_APB can be found in the related links. Related Links 15. MCLK – Main Clock 15.6.2.6 Peripheral Clock Masking 27.4.4 DMA Not applicable. 27.4.5 Interrupts The interrupt request line is connected to the Interrupt Controller.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.5 Functional Description 27.5.1 Principle of Operation The Peripheral Access Control module allows the user to set a write protection on peripheral modules and generate an interrupt in case of a peripheral access violation. The peripheral’s protection can be set, cleared or locked at the user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the peripherals.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller value that defines the operation to be done on the control access bit. These operations can be “clear protection”, “set protection” and “set and lock protection bit”. The “clear protection” operation will remove the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.6 Offset Register Summary Name 0x00 WRCTRL 0x04 EVCTRL Bit Pos. 7:0 PERID[7:0] 15:8 PERID[15:8] 23:16 KEY[7:0] 31:24 7:0 ERREO 0x05 ... Reserved 0x07 0x08 INTENCLR 7:0 ERR 0x09 INTENSET 7:0 ERR 0x0A ...
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller ...........continued Offset Name Bit Pos. 7:0 0x38 STATUSB EVSYS 15:8 TC3 DMAC PORT CMCC NVMCTRL DSU TC2 TCC1 TCC0 SERCOM3 SERCOM2 23:16 USB RAMECC 31:24 7:0 0x3C STATUSC PDEC 15:8 TC5 TC4 TCC3 TCC2 GMAC CAN1 CAN0 CCL QSPI PUKCC ICM TRNG AES AC TC7 TC6 TCC4 SERCOM7 SERCOM6 SERCOM5 SERCOM4 PCC I2S DAC ADC1 23:16 31:24 7:0 0x40 STATUSD ADC0 15:8 23:16 31:24 27.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller ...........continued Periph. Bridge Name BridgeNumber PERID Values D 3 96+N E 4 128+N © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.2 Event Control Name: Offset: Reset: Property: Bit 7 EVCTRL 0x04 0x00 - 6 5 4 3 2 1 0 ERREO Access RW Reset 0 Bit 0 – ERREO Peripheral Access Error Event Output This bit indicates if the Peripheral Access Error Event Output is enabled or disabled.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.3 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x08 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.4 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x09 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENCLR).
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.5 Bridge Interrupt Flag Status Name: Offset: Reset: Property: INTFLAGAHB 0x10 0x00000000 - These flags are cleared by writing a '1' to the corresponding bit. These flags are set when an access error is detected by the corresponding AHB slave, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 11 – PUKCC Interrupt Flag for PUKCC This flag is set when an access error is detected by the PUKCC AHB slave, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' has no effect. Writing a '1' to this bit will clear the PUKCC interrupt flag. Bit 10 – HPB3 Interrupt Flag for HPB3 This flag is set when an access error is detected by the HPB3 AHB slave, and will generate an interrupt request if INTENCLR/SET.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 3 – RAMCM4S Interrupt Flag for RAMCM4S This flag is set when an access error is detected by the RAMCM4S AHB slave, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' has no effect. Writing a '1' to this bit will clear the RAMCM4S interrupt flag.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.6 Peripheral Interrupt Flag Status - Bridge A Name: Offset: Reset: Property: INTFLAGA 0x14 0x00000000 – These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to these bits has no effect. Writing a '1' to these bits will clear the corresponding INTFLAGx interrupt flag.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 12 – SERCOM0 Interrupt Flag for SERCOM0 This bit is set when a Peripheral Access Error occurs while accessing the SERCOM0, and will generate an interrupt request if SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the flag. Bit 11 – FREQM Interrupt Flag for FREQM This bit is set when a Peripheral Access Error occurs while accessing the FREQM, and will generate an interrupt request if SET.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 4 – OSCCTRL Interrupt Flag for OSCCTRL This bit is set when a Peripheral Access Error occurs while accessing the OSCCTRL, and will generate an interrupt request if SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the flag. Bit 3 – RSTC Interrupt Flag for RSTC This bit is set when a Peripheral Access Error occurs while accessing the RSTC, and will generate an interrupt request if SET.ERR is '1'.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.7 Peripheral Interrupt Flag Status - Bridge B Name: Offset: Reset: Property: INTFLAGB 0x18 0x00000000 – These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to these bits has no effect. Writing a '1' to these bits will clear the corresponding INTFLAGx interrupt flag.
PAGE 744
SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 12 – TCC1 Interrupt Flag for TCC1 This flag is set when a Peripheral Access Error occurs while accessing the TCC1, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the TCC1 interrupt flag.
PAGE 745
SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 2 – NVMCTRL Interrupt Flag for NVMCTRL This flag is set when a Peripheral Access Error occurs while accessing the NVMCTRL, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the NVMCTRL interrupt flag.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.8 Peripheral Interrupt Flag Status - Bridge C Name: Offset: Reset: Property: INTFLAGC 0x1C 0x00000000 – These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to these bits has no effect. Writing a '1' to these bits will clear the corresponding INTFLAGx interrupt flag.
PAGE 747
SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 11 – ICM Interrupt Flag for ICM This flags is set when a Peripheral Access Error occurs while accessing the peripheral associated with the ICM, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the ICM interrupt flag.
PAGE 748
SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 2 – GMAC Interrupt Flag for GMAC This flags is set when a Peripheral Access Error occurs while accessing the peripheral associated with the GMAC, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the GMAC interrupt flag.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.9 Peripheral Interrupt Flag Status - Bridge D Name: Offset: Reset: Property: INTFLAGD 0x20 0x00000000 – These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to these bits has no effect. Writing a '1' to these bits will clear the corresponding INTFLAGx interrupt flag.
PAGE 750
SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 8 – ADC1 Interrupt Flag for ADC1 This flag is set when a Peripheral Access Error occurs while accessing the ADC1, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to these bits has no effect. Writing a '1' to these bits will clear the ADC1 interrupt flag.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 0 – SERCOM4 Interrupt Flag for SERCOM4 This flag is set when a Peripheral Access Error occurs while accessing the SERCOM4, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to these bits has no effect. Writing a '1' to these bits will clear the SERCOM4 interrupt flag. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.10 Peripheral Write Protection Status A Name: Offset: Reset: Property: STATUSA 0x34 0x00010000 PAC Write-Protection Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Bit Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 12 – SERCOM0 SERCOM0 APB Protect Enable Value Description 0 SERCOM0 is not write protected 1 SERCOM0 is write protected Bit 11 – FREQM FREQM APB Protect Enable Value Description 0 FREQM is not write protected 1 FREQM is write protected Bit 10 – EIC EIC APB Protect Enable Value Description 0 EIC is not write protected 1 EIC is write protected Bit 8 – WDT WDT APB Protect Enable Value Description 0 WDT is not write protected 1 WDT is write pr
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 1 – PM Value 0 1 PM APB Protect Enable Description PM is not write protected PM is write protected Bit 0 – PAC PAC APB Protect Enable Value Description 0 PAC is not write protected 1 PAC is write protected © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.11 Peripheral Write Protection Status - Bridge B Name: Offset: Reset: Property: STATUSB 0x38 0x00000002 PAC Write-Protection Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Bit Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 12 – TCC1 TCC1 APB Protect Enable Value Description 0 TCC1 peripheral is not write protected 1 TCC1 peripheral is write protected Bit 11 – TCC0 TCC0 APB Protect Enable Value Description 0 TCC0 peripheral is not write protected 1 TCC0 peripheral is write protected Bit 10 – SERCOM3 SERCOM3 APB Protect Enable Value Description 0 SERCOM3 peripheral is not write protected 1 SERCOM3 peripheral is write protected Bit 9 – SERCOM2 SERCOM2 APB Prote
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 0 – USB USB APB Protect Enable Value Description 0 USB peripheral is not write protected 1 USB peripheral is write protected © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.12 Peripheral Write Protection Status - Bridge C Name: Offset: Reset: Property: STATUSC 0x3C 0x00000000 PAC Write-Protection Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Bit Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 11 – ICM ICM APB Protection Enable Value Description 0 Peripheral is not write protected 1 Peripheral is write protected Bit 10 – TRNG TRNG APB Protection Enable Value Description 0 Peripheral is not write protected 1 Peripheral is write protected Bit 9 – AES AES APB Protection Enable Value Description 0 Peripheral is not write protected 1 Peripheral is write protected Bit 8 – AC Value 0 1 AC APB Protection Enable Description Peripheral i
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 1 – CAN1 CAN1 APB Protection Enable Value Description 0 Peripheral is not write protected 1 Peripheral is write protected Bit 0 – CAN0 CAN0 APB Protection Enable Value Description 0 Peripheral is not write protected 1 Peripheral is write protected © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller 27.7.13 Peripheral Write Protection Status - Bridge D Name: Offset: Reset: Property: STATUSD 0x40 0x00000000 PAC Write-Protection, Read-Only Writing to this register has no effect. Reading STATUS register returns peripheral write protection status: Bit Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected.
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SAM D5x/E5x Family Data Sheet PAC - Peripheral Access Controller Bit 8 – ADC1 ADC1 APB Protect Enable Value Description 0 ADC1 is not write protected 1 ADC1 is write protected Bit 7 – ADC0 ADC0 APB Protect Enable Value Description 0 ADC0 is not write protected 1 ADC0 is write protected Bit 6 – TC7 TC7 APB Protect Enable Value Description 0 TC7 is not write protected 1 TC7 is write protected Bit 5 – TC6 TC6 APB Protect Enable Value Description 0 TC6 is not write protected 1 TC6 is write protected Bit 4 – TCC
PAGE 763
SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28. OSCCTRL – Oscillators Controller 28.1 Overview The Oscillators Controller (OSCCTRL) provides a user interface to the XOSCn, DFLL48M, and two FDPLL200M. Through the interface registers, it is possible to enable, disable, calibrate, and monitor the oscillators. The status of all oscillators are collected in the Status register (STATUS).
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.3 Block Diagram Figure 28-1. OSCCTRL Block Diagram XOUT[1:0] XIN[1:0] 2 OSCCTRL 2 CFD Event0 CLK_XOSC0 XOSC CFD CLK_XOSC1 XOSC CFD CLK_DFLL48M OSCILLATORS CONTROL CFD Event1 DFLL48M CLK_DPLL0 FDPLL200M CLK_DPLL1 FDPLL200M STATUS INTERRUPTS GENERATOR 28.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller The DFLL48M requires a reference clock (GCLK_DFLL48M_REF) from the GCLK. The control logic uses the oscillator output, which is also asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details. The FDPLL200Mn require a reference clock (GCLK_DPLL) for the FDPLL output.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller The Status register gathers different status signals coming from the oscillators controlled by the OSCCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from Sleep mode, provided the corresponding interrupt is enabled. 28.6.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller ...........continued XOSCCTRLn.RUNS TDBY XOSCCTRLn.ONDE XOSCTRLn.ENABL MAND E Sleep Behavior 1 0 1 Always run in Idle and Standby Sleep modes. 1 1 1 Only run in Idle or Standby Sleep modes if requested by a peripheral. After a hard reset, or when waking up from a sleep mode where the XOSCn was disabled, the XOSCn will need a certain amount of time to stabilize on the correct frequency.
PAGE 768
SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller (INTFLAG.CLKFAILn) is set. If the CLKFAILn bit in the Interrupt Enable Set register (INTENSET.CLKFAILn) is set, an interrupt is generated . An output event is generated as well, if the Event Output enable bit in the Event Control register (EVCTRL.CFDEOn) is set. The XOSCn clock continues to be monitored after a clock failure. The Clock Failure status bit in the Status register (STATUS.CLKFAILn) reflects the current XOSCn clock activity.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.6.4.1 Basic Operation Operating modes The DFLL48M will behave differently in different sleep modes based on the settings of DFLLCTRLA.RUNSTDBY, DFLLCTRLA.ONDEMAND and DFLLCTRLA.ENABLE, as shown in the following table. Table 28-2. DFLL48M Sleep Behavior DFLLCTRLA.RUNSTD BY DFLLCTRLA.ONDEMA ND DFLLCTRLA.ENABLE Sleep Behavior - - 0 Disabled 0 0 1 Always run in Idle Sleep modes. Run in Standby Sleep mode if requested by a peripheral.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 1. 2. 3. 4. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0 (DFLL48M_Reference). Refer to GCLK for details. Select the maximum step size allowed in finding the Coarse and Fine values by writing the appropriate values to the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and DFLLMUL. FSTEP) in the DFLL Multiplier register.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller stored in the DFLL Multiplication Ratio Difference bit group (DFLLVAL.DIFF) in the DFLL Value register. The relative error on CLK_DFLL48M compared to the target frequency is calculated as follows: ERROR = DIFF MUL Drift Compensation If the Stable DFLL Frequency bit (DFLLCTRLB.STABLE) in the DFLL Control register is zero, the frequency tuner will automatically compensate for drift in the CLK_DFLL48M without losing either of the locks.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller USB Clock Recovery Mode USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). This mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit in DFLL Control register (DFLLCTRLB.USBCRM and DFLLCTRLB.MODE). In USB Clock Recovery mode, the status bits of the DFLL in OSCCTRL.STATUS are determined by the USB bus activity, and have no valid meaning.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller • XOSC0 and XOSC1: These clocks are provided by the External Multipurpose Crystal Oscillator (XOSC). • GCLK: This clock is provided by the Generic Clock Controller.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Figure 28-3. Enable synchronization busy operation CLK_APB_OSCCTRL ENABLE CK SYNCBUSY.ENABLE The frequency of the DPLLCn output clock CLK_DPLLn is stable when the module is enabled and when the LOCK bit is set. When DPLLnCTRLB.LTIME is different from 0, a user defined lock time is used to validate the lock operation. In that case the lock time is constant. If DPLLnCTRLB.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Figure 28-5. CK and CLK_DPLL output from DPLL off mode to running mode when wake up fast is activated CKR ENABLE CK CLK_DPLL LOCK t startup_time t lock_time CK STABLE Figure 28-6. CK and CLK_DPLL output from running mode to DPLLC off mode. CKR ENABLE CK CLK_DPLL LOCK Operating modes The DPLLn will behave differently in different sleep modes based on the settings of DPLLnCTRLA.RUNSTDBY, DPLLnCTRLA.ONDEMAND and DPLLnCTRLA.ENABLE. Table 28-5.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Reference Clock Switching When a software operation requires reference clock switching, the normal operation is to disable the DPLLn, modify the DPLLnCTRLB.REFCLK to select the desired reference source and activate the DPLLn again. The CLK_DPLLn output clock is ready when DPLLnSTATUS.CLKRDY bit is set. XOSC Reference Clock Divider DPLLnCTRLB.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Digital Filter Selection The digital filter selection can be changed from the filter selection register DPLLnCTRLB.FILTER. The DPLL digital filter coefficients are automatically adjusted in order to provide a good compromise between stability and jitter. For more information, refer to DPLLnCTRLB. Sigma-Delta DCO Filter Selection The sigma-delta DAC low pass filter can be controlled and adjusted from the DCO filter selection register DPLLnCTRLB.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.6.9 Synchronization Due to the multiple clock domains, some registers in the DFLL48M must be synchronized when accessed. A register can require: • Synchronization when written • Synchronization when read • No synchronization When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization Busy register (DFLLSYNC) will be set immediately, and cleared when synchronization is complete.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.7 Register Summary Offset Name Bit Pos. 0x00 EVCTRL 7:0 CFDEO1 CFDEO0 0x01 ...
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller ...........continued Offset 0x28 Name DFLLMUL Bit Pos. 7:0 MUL[7:0] 15:8 MUL[15:8] 23:16 FSTEP[7:0] 31:24 0x2C DFLLSYNC CSTEP[5:0] 7:0 DFLLMUL DFLLVAL DFLLCTRLB ENABLE 0x2D ... Reserved 0x2F 0x30 DPLL0CTRLA 7:0 ONDEMAND RUNSTDBY ENABLE 0x31 ...
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller ...........continued Offset Name Bit Pos. 7:0 0x54 DPLL1STATUS CLKRDY LOCK 15:8 23:16 31:24 28.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.2 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x04 0x00000000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Writing a zero to this bit has no effect. Writing a '1' to this bit will clear the DPLL1 Lock Fall Interrupt Enable bit, which disables the DPLL1 Lock Fall interrupt. Bit 24 – DPLL1LCKR DPLL1 Lock Rise Interrupt Enable 0: The DPLL1 Lock Rise interrupt is disabled. 1: The DPLL1 Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL1 Lock Rise Interrupt flag is set. Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Writing a '1' to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt. Bit 11 – DFLLLCKC DFLL Lock Coarse Interrupt Enable 0: The DFLL Lock Coarse interrupt is disabled. 1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set. Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.3 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x08 0x00000000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Writing a zero to this bit has no effect. Writing a '1' to this bit will set the DPLL1 Lock Fall Interrupt Enable bit, which enables the DPLL1 Lock Fall interrupt. Bit 24 – DPLL1LCKR DPLL1 Lock Rise Interrupt Enable 0: The DPLL1 Lock Rise interrupt is disabled. 1: The DPLL1 Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL1 Lock Rise Interrupt flag is set. Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Writing a '1' to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL Reference Clock Stopped interrupt. Bit 11 – DFLLLCKC DFLL Lock Coarse Interrupt Enable 0: The DFLL Lock Coarse interrupt is disabled. 1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set. Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Bit 24 – DPLL1LCKR DPLL1 Lock Rise This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the DPLL1 Lock Rise bit in the Status register (STATUS. DPLL1LCKR) and will generate an interrupt request if INTENSET.DPLL1LCKR is '1'. Writing a zero to this bit has no effect. Writing a '1' to this bit clears the DPLL1 Lock Rise interrupt flag.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Bit 10 – DFLLLCKF DFLL Lock Fine This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (STATUS.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is '1'. Writing a zero to this bit has no effect. Writing a '1' to this bit clears the DFLL Lock Fine interrupt flag. Bit 9 – DFLLOOB DFLL Out Of Bounds This flag is cleared by writing a '1' to it.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Bit 17 – DPLL0LCKF DPLL0 Lock Fall 0: DPLL0 Lock fall edge not detected. 1: DPLL0 Lock fall edge detected. Bit 16 – DPLL0LCKR DPLL0 Lock Rise 0: DPLL0 Lock rise edge not detected. 1: DPLL0 Lock rise edge detected. Bit 12 – DFLLRCS DFLL Reference Clock Stopped 0: DFLL reference clock is running. 1: DFLL reference clock has stopped. Bit 11 – DFLLLCKC DFLL Lock Coarse 0: No DFLL coarse lock detected. 1: DFLL coarse lock detected.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 1: XOSC0 is stable and ready to be used as a clock source. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.6 External Multipurpose Crystal Oscillator Control Name: Offset: Reset: Property: Bit XOSCCTRL 0x14 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller ...........
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Table 28-7. External Multipurpose Crystal Oscillator Current Settings Current Setting Frequency Range IMULT[3:0] IPTAT[1:0] 24MHz to 48MHz 6 3 16MHz to 24MHz 5 3 8MHz to 16MHz 4 3 8MHz 3 2 For relatively small CLOAD in a frequency range, the setting for the lower frequency range can be used to preserve current consumption. Bit 8 – LOWBUFGAIN Low Buffer Gain Enable 0: The low buffer gain of oscillator XOSCn is disabled.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller Bit 1 – ENABLE Oscillator Enable 0: The oscillator XOSCn is disabled. 1: The oscillator XOSCn is enabled. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.7 DFLL48M Control A Name: Offset: Reset: Property: Bit Access Reset DFLLCTRLA 0x1C 0x82 PAC Write-Protection 7 6 5 4 3 2 1 ONDEMAND RUNSTDBY ENABLE R/W R/W R/W 1 0 1 0 Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the DFLL to be enabled or disabled depending on peripheral clock requests. If On Demand is set, the DFLL will only be running when requested by a peripheral and enabled (DFLLTRLA.
PAGE 800
SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.8 DFLL48M Control B Name: Offset: Reset: Property: Bit Access Reset DFLLCTRLB 0x20 0x00 Read-Synchronized 7 6 5 4 3 2 1 0 WAITLOCK BPLCKC QLDIS CCDIS USBCRM LLAW STABLE MODE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – WAITLOCK Wait Lock This bit controls the DFLL output clock, depending on lock status: 0: Output clock before the DFLL is locked. 1: Output clock when DFLL is locked (Fine lock).
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.11 DFLL48M Synchronization Name: Offset: Reset: Bit 7 DFLLSYNC 0x2C 0x00 6 5 4 3 2 1 DFLLMUL DFLLVAL DFLLCTRLB ENABLE Access R R R R Reset 0 0 0 0 0 Bit 4 – DFLLMUL DFLLMUL Synchronization Busy This bit is cleared when the synchronization of DFLLMUL register between the clock domains is complete. This bit is set when the synchronization of DFLLMUL register between clock domains is started.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.12 DPLL Control A Name: Offset: Reset: Property: Bit Access Reset DPLLCTRLA 0x30 + n*0x14 [n=0..1] 0x80 PAC Write-Protection, Write-Synchronized(ENABLE), Enable-Protected (ONDEMAND, RUNSTDBY) 7 6 ONDEMAND RUNSTDBY 5 4 3 2 ENABLE 1 R/W R/W R/W 1 0 0 0 Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the DPLLn to be enabled or disabled, depending on peripheral clock requests.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.13 DPLL Ratio Control Name: Offset: Reset: Property: DPLLRATIO 0x34 + n*0x14 [n=0..1] 0x00000000 PAC Write-Protection, Write-Synchronized Refer to the Synchronization section in the Clock System Overview chapter for details on the functionality of this register.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.14 DPLL Control B Name: Offset: Reset: Property: Bit DPLLCTRLB 0x38 + n*0x14 [n=0..
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller ...........continued DCOFILTER[2:0] Capacitor (pF) Bandwidth Fn (MHz) 0x5 3 0.55 0x6 3.5 0.45 0x7 4 0.4 Bit 11 – LBYPASS Lock Bypass Bits 10:8 – LTIME[2:0] Lock Time Write these bits to select the lock time-out value, as shown in the figure below: Value Name Description 0x0 Default No time-out. Automatic lock.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller ...........continued FILTER[3:0] PLL Bandwidth (fn) Damping Factor 0x6 65.6 kHz 0.28 0x7 92.7 kHz 0.39 0x8 46.4 kHz 1.49 0x9 65.6 kHz 2.11 0xA 23.2 kHz 0.75 0xB 32.8 kHz 1.06 0xC 65.6 kHz 1.07 0xD 92.7 kHz 1.51 0xE 32.8 kHz 0.53 0xF 46.4 kHz 0.75 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.15 DPLL Synchronization Busy Name: Offset: Reset: Bit DPLLSYNCBUSY 0x3C + n*0x14 [n=0..1] 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 Access Reset Bit Access Reset Bit Access Reset Bit 2 1 DPLLRATIO ENABLE Access R R Reset 0 0 Bit 2 – DPLLRATIO DPLL Loop Divider Ratio Synchronization Status 0: The DPLLRATIO register has been synchronized.
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SAM D5x/E5x Family Data Sheet OSCCTRL – Oscillators Controller 28.8.16 DPLL Status Name: Offset: Reset: Bit DPLLSTATUS 0x40 + n*0x14 [n=0..1] 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Access Reset Bit Access Reset Bit Access Reset Bit 1 0 CLKRDY LOCK Access R R Reset 0 0 Bit 1 – CLKRDY DPLL Clock Ready 0: The DPLLn output clock is off. 1: The DPLLn output clock in on.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29. 29.1 OSC32KCTRL – 32KHz Oscillators Controller Overview The 32KHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768kHz oscillators: XOSC32K and OSCULP32K. The OSC32KCTRL sub-peripherals can be enabled, disabled, calibrated, and monitored through interface registers. All sub-peripheral statuses are collected in the Status register (STATUS).
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.3 Block Diagram XOUT32 XIN32 OSC32KCTRL 32K OSCILLATORS CONTROL CFD Event CFD CFD CLK_XOSC32K XOSC32K CLK_RTC RTCCTRL CLK_OSCULP32K OSCULP32K STATUS INTERRUPTS 29.4 Interrupts Signal Description Signal Description Type XIN32 Analog Input 32.768 kHz Crystal Oscillator or external clock input XOUT32 Analog Output 32.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.5.2 Power Management The OSC32KCTRL will continue to operate in any sleep mode where a 32KHz oscillator is running as source clock. The OSC32KCTRL interrupts can be used to wake up the device from sleep modes. Related Links 18. PM – Power Manager 29.5.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.6 Functional Description 29.6.1 Principle of Operation XOSC32K and OSCULP32K are configured via OSC32KCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled, or have their calibration values updated. The STATUS register gathers different status signals coming from the sub-peripherals of OSC32KCTRL.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller Table 29-1. XOSC32K Sleep Behavior CPU Mode XOSC32K. XOSC32K.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller Clock Failure Detection The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC32K clock when the oscillator is disabled (XOSC32K.ENABLE=0). Before starting CFD operation, the user must start and enable the safe clock source (OSCULP32K oscillator). CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (CFDCTRL.CFDEN).
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller Event If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Sleep Mode The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For further details, refer to the Sleep Behavior table above.
PAGE 818
SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller • XOSC32KRDY - 32KHz Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSC32KRDY bit is detected • XOSC32KFAIL - Clock Failure Detector: A 0-to-1 transition on the STATUS.XOSC32KFAIL bit is detected All these interrupts are synchronous wake-up source. Each interrupt source has an interrupt flag associated with it.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.7 Offset Register Summary Name Bit Pos. 7:0 0x00 INTENCLR XOSC32KFAI XOSC32KRD L Y XOSC32KFAI XOSC32KRD L Y XOSC32KFAI XOSC32KRD L Y XOSC32KFAI XOSC32KRD L Y 15:8 23:16 31:24 7:0 0x04 INTENSET 15:8 23:16 31:24 7:0 0x08 INTFLAG 15:8 23:16 31:24 7:0 0x0C STATUS XOSC32KSW 15:8 23:16 31:24 0x10 RTCCTRL 7:0 RTCSEL[2:0] 0x11 ...
PAGE 820
SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. Related Links 27. PAC - Peripheral Access Controller © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.1 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x00 0x00000000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 822
SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.2 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x04 0x00000000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.3 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit INTFLAG 0x08 0x00000000 – 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 0 XOSC32KFAIL XOSC32KRDY R/W R/W 0 0 Bit 2 – XOSC32KFAIL XOSC32K Clock Failure Detector This flag is cleared by writing a '1' to it.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.4 Status Name: Offset: Reset: Property: Bit STATUS 0x0C 0x00000000 – 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit XOSC32KSW XOSC32KFAIL 0 XOSC32KRDY Access R R R Reset 0 0 0 Bit 3 – XOSC32KSW XOSC32K Clock Switch Value Description 0 XOSC32K is not switched and provided the crystal oscillator.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.5 RTC Clock Selection Control Name: Offset: Reset: Property: Bit 7 RTCCTRL 0x10 0x00 PAC Write-Protection 6 5 4 3 2 1 0 RTCSEL[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – RTCSEL[2:0] RTC Clock Selection These bits select the source for the RTC. Value Name Description 0x0 ULP1K 1.024kHz from 32KHz internal ULP oscillator 0x1 ULP32K 32.768kHz from 32KHz internal ULP oscillator 0x2, Reserved 0x3 0x4 XOSC1K 1.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller Note: 1. Actual Start-Up time is 1 OSCULP32K cycle + 3 XOSC32K cycles. 2. The given time assumes an XTAL frequency of 32.768kHz. Bit 7 – ONDEMAND On Demand Control This bit controls how the XOSC32K behaves when a peripheral clock request is detected. For details, refer to Table 29-1. Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC32K behaves during standby sleep mode. For details, refer to Table 29-1.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.7 Clock Failure Detector Control Name: Offset: Reset: Property: Bit 7 CFDCTRL 0x16 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 CFDPRESC SWBACK CFDEN R/W R/W R/W 0 0 0 Bit 2 – CFDPRESC Clock Failure Detector Prescaler This bit selects the prescaler for the Clock Failure Detector.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.8 Event Control Name: Offset: Reset: Property: Bit 7 EVCTRL 0x17 0x00 PAC Write-Protection 6 5 4 3 2 1 0 CFDEO Access R/W Reset 0 Bit 0 – CFDEO Clock Failure Detector Event Out Enable This bit controls whether the Clock Failure Detector event output is enabled and an event will be generated when the CFD detects a clock failure.
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SAM D5x/E5x Family Data Sheet OSC32KCTRL – 32KHz Oscillators Controller 29.8.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30. FREQM – Frequency Meter 30.1 Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 30.2 Features • • • • 30.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.5.1 I/O Lines The GCLK I/O lines (GCLK_IO[7:0]) can be used as measurement or reference clock sources. This requires the I/O pins to be configured. 30.5.2 Power Management The FREQM will continue to operate in idle sleep mode where the selected source clock is running. The FREQM’s interrupts can be used to wake up the device from idle sleep mode. Refer to the Power Manager chapter for details on the different sleep modes. Related Links 18.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter • Control B register (CTRLB) • Interrupt Flag Status and Clear register (INTFLAG) • Status register (STATUS) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links 27. PAC - Peripheral Access Controller 30.6 Functional Description 30.6.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter The FREQM is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). On software reset, all registers in the FREQM will be reset to their initial state, and the FREQM will be disabled. Then ENABLE and SWRST bits are write-synchronized. Related Links 30.6.7 Synchronization 30.6.2.3 Measurement In the Configuration A register, the Number of Reference Clock Cycles field (CFGA.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter This interrupt is a synchronous wake-up source. Note that interrupts must be globally enabled for interrupt requests to be generated. 30.6.5 Events Not applicable. 30.6.6 Sleep Mode Operation The FREQM will continue to operate in idle sleep mode where the selected source clock is running. The FREQM’s interrupts can be used to wake up the device from idle sleep mode.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 CTRLB 7:0 0x02 CFGA 7:0 ENABLE SWRST START REFNUM[7:0] 15:8 0x04 ... Reserved 0x07 0x08 INTENCLR 7:0 DONE 0x09 INTENSET 7:0 DONE 0x0A INTFLAG 7:0 0x0B STATUS 7:0 OVF BUSY 7:0 ENABLE SWRST 0x0C SYNCBUSY DONE 15:8 23:16 31:24 0x10 VALUE 7:0 VALUE[7:0] 15:8 VALUE[15:8] 23:16 VALUE[23:16] 31:24 30.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 ENABLE SWRST R/W R/W 0 0 Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.2 Control B Name: Offset: Reset: Property: Bit 7 CTRLB 0x01 0x00 – 6 5 4 3 2 1 0 START Access W Reset 0 Bit 0 – START Start Measurement Value Description 0 Writing a '0' has no effect. 1 Writing a '1' starts a measurement. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.3 Configuration A Name: Offset: Reset: Property: Bit CFGA 0x02 0x0000 PAC Write-Protection, Enable-protected 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset Bit REFNUM[7:0] Access Reset Bits 7:0 – REFNUM[7:0] Number of Reference Clock Cycles Selects the duration of a measurement in number of CLK_FREQM_REF cycles. This must be a non-zero value, i.e.
PAGE 840
SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: Bit 7 INTENCLR 0x08 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Measurement Done Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Measurement Done Interrupt Enable bit, which disables the Measurement Done interrupt. Value Description 0 The Measurement Done interrupt is disabled.
PAGE 841
SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.5 Interrupt Enable Set Name: Offset: Reset: Property: Bit 7 INTENSET 0x09 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Measurement Done Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Measurement Done Interrupt Enable bit, which enables the Measurement Done interrupt. Value Description 0 The Measurement Done interrupt is disabled.
PAGE 842
SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x0A 0x00 – 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Mesurement Done This flag is cleared by writing a '1' to it. This flag is set when the STATUS.BUSY bit has a one-to-zero transition. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the DONE interrupt flag. © 2019 Microchip Technology Inc.
PAGE 843
SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.7 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x0B 0x00 – 6 5 4 3 Access Reset 2 1 0 OVF BUSY R/W R 0 0 Bit 1 – OVF Sticky Count Value Overflow This bit is cleared by writing a '1' to it. This bit is set when an overflow condition occurs to the value counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the OVF status.
PAGE 844
SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.8 Synchronization Busy Name: Offset: Reset: Property: Bit SYNCBUSY 0x0C 0x00000000 – 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Access Reset Bit Access Reset Bit Access Reset Bit 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Enable This bit is cleared when the synchronization of CTRLA.ENABLE is complete. This bit is set when the synchronization of CTRLA.
PAGE 845
SAM D5x/E5x Family Data Sheet FREQM – Frequency Meter 30.8.
PAGE 846
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31. 31.1 EVSYS – Event System Overview The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that respond to events are called event users.
PAGE 847
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.3 Block Diagram Figure 31-1. Event System Block Diagram Clock Request [n:0] Event Channel n Event Channel 1 USER m+1 USER m Event Channel 0 Asynchronous Path USERm.CHANNEL CHANNEL0.PATH SleepWalking Detector Synchronized Path Edge Detector PERIPHERAL0 Channel_EVT_n EVT D Q To Peripheral x R EVT ACK PERIPHERAL x Channel_EVT_0 Q D Q D Q D Peripheral x Event Acknowledge Resynchronized Path R CHANNEL0.EVGEN SWEVT.CHANNEL0 CHANNEL0.
PAGE 848
SAM D5x/E5x Family Data Sheet EVSYS – Event System Important: Only EVSYS channel 0 to 11 can be configured as synchronous or resynchronized. Related Links 15.6.2.6 Peripheral Clock Masking 14. GCLK - Generic Clock Controller 31.4.4 DMA Not applicable. 31.4.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the EVSYS interrupts requires the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links 10.
PAGE 849
SAM D5x/E5x Family Data Sheet EVSYS – Event System When using synchronous or resynchronized path, the Event System includes options to transfer events to users when rising, falling or both edges are detected on event generators. For further details, refer to the Channel Path section of this chapter. Related Links 31.5.2.6 Channel Path 31.5.2 Basic Operation 31.5.2.
PAGE 850
SAM D5x/E5x Family Data Sheet EVSYS – Event System the Event System to generate internal events when rising, falling or both edges are detected on the selected event generator. An event channel is able to generate internal events for the specific software commands. A channel block diagram is shown in Block Diagram section. Related Links 31.3 Block Diagram 31.5.2.5 Event Generators Each event channel can receive the events form all event generators.
PAGE 851
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.5.2.7 Edge Detection When synchronous or resynchronized paths are used, edge detection must be enabled. The event system can execute edge detection in three different ways: • Generate an event only on the rising edge • Generate an event only on the falling edge • Generate an event on rising and falling edges. Edge detection is selected by writing to the Edge Selection bit group of the Channel register (CHANNELn.EDGSEL). 31.5.2.
PAGE 852
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.5.2.12 Software Event A software event can be initiated on a channel by writing a '1' to the Software Event bit in the Channel register (CHANNELm.SWEVT). Then the software event can be serviced as any event generator; i.e., when the bit is set to ‘1’, an event will be generated on the respective channel. 31.5.2.13 Interrupt Status and Interrupts Arbitration The Interrupt Status register stores all channels with pending interrupts, as shown below.
PAGE 853
SAM D5x/E5x Family Data Sheet EVSYS – Event System Figure 31-3. Static Priority Lowest Channel Channel 0 Highest Priority . . . Channel x Channel x+1 . . . Highest Channel Lowest Priority Channel N The dynamic arbitration scheme available in the Event System is round-robin. Round-robin arbitration is enabled by writing PRICTRL.RREN to one.
PAGE 854
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.5.3 Interrupts The EVSYS has the following interrupt sources for each channel: • Overrun Channel n interrupt (OVR) • Event Detected Channel n interrupt (EVD) These interrupts events are asynchronous wake-up sources. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the corresponding Channel n Interrupt Flag Status and Clear (CHINTFLAG) register is set when the interrupt condition occurs.
PAGE 855
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued CHANNELn.PAT H CHANNELn. ONDEMAND CHANNELn. RUNSTDBY SYNC/RESYNC 1 0 Only run in IDLE sleep modes if an event must be propagated. Disabled in STANDBY sleep mode. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally. SYNC/RESYNC 1 1 Run in both IDLE and STANDBY sleep modes. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally.
PAGE 856
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.6 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 SWRST 0x01 ...
PAGE 857
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Offset Name Bit Pos.
PAGE 858
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Offset Name Bit Pos.
PAGE 859
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Offset Name Bit Pos.
PAGE 860
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Offset Name Bit Pos.
PAGE 861
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Offset Name Bit Pos.
PAGE 862
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Offset Name Bit Pos.
PAGE 863
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.4.8 Register Access Protection © 2019 Microchip Technology Inc.
PAGE 864
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection 6 5 4 3 2 1 0 SWRST Access W Reset 0 Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the EVSYS to their initial state. It will always take precedence, meaning that all other writes in the same write-operation will be discarded.
PAGE 865
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.
PAGE 866
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.
PAGE 867
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.4 Channel Pending Interrupt Name: Offset: Reset: INTPEND 0x10 0x4000 An interrupt that handles several channels should consult the INTPEND register to find out which channel number has priority (ignoring/filtering each channel that has its own interrupt line). An interrupt dedicated to only one channel must not use the INTPEND register.
PAGE 868
SAM D5x/E5x Family Data Sheet EVSYS – Event System Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn) of this peripheral, where n is determined by the Channel ID bit field (ID) in this register. Bits 4:0 – ID[4:0] Channel ID These bits store the channel number of the highest priority. When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.
PAGE 869
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.
PAGE 870
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.
PAGE 871
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.
PAGE 872
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.8 Channel n Control Name: Offset: Reset: Property: CHANNEL 0x20 + n*0x08 [n=0..31] 0x00008000 PAC Write-Protection This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.
PAGE 873
SAM D5x/E5x Family Data Sheet EVSYS – Event System Value 0x2 Name FALLING_EDGE 0x3 BOTH_EDGES Description Event detection only on the falling edge of the signal from the event generator Event detection on rising and falling edges of the signal from the event generator Bits 9:8 – PATH[1:0] Path Selection These bits are used to choose which path will be used by the selected channel. Note: The path choice can be limited by the channel source, see the table in 31.7.13 USERm.
PAGE 874
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Value Name Description 0x33 TCC1_TRG TCC1 Trigger Event 0x34 TCC1_CNT TCC1 Counter 0x35 - 0x38 TCC1_MCx TCC1 Match/Compare x=0..3 0x39 TCC2_OVF TCC2 Overflow 0x3A TCC2_TRG TCC2 Trigger Event 0x3B TCC2_CNT TCC2 Counter 0x3C - 0x3E TCC2_MCx TCC2 Match/Compare x=0..2 0x3F TCC3_OVF TCC3 Overflow 0x40 TCC3_TRG TCC3 Trigger Event 0x41 TCC3_CNT TCC3 Counter 0x42 - 0x43 TCC3_MCx TCC3 Match/Compare x=0..
PAGE 875
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued Value Name Description 0x61 PDEC_OVF PDEC Overflow 0x62 PDEC_ERR PDEC Error 0x63 PDEC_DIR PDEC Direction 0x64 PDEC_VLC PDEC VLC 0x65 - 0x66 PDEC_MCx PDEC MCx x=0..1 0x67 ADC0_RESRDY ADC0 RESRDY 0x68 ADC0_WINMON ADC0 Window Monitor 0x69 ADC1_RESRDY ADC1 RESRDY 0x6A ADC1_WINMON ADC1 Window Monitor 0x6B - 0x6C AC_COMPx AC Comparator, x=0..1 0x6D AC_WIN AC0 Window 0x6E - 0x6F DAC_EMPTYx DAC empty, x=0..
PAGE 876
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.9 Channel n Interrupt Enable Clear Name: Offset: Reset: Property: Bit 7 CHINTENCLR 0x24 + n*0x08 [n=0..31] 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 EVD OVR RW RW 0 0 Bit 1 – EVD Channel Event Detected Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Event Detected Channel Interrupt Enable bit, which disables the Event Detected Channel interrupt.
PAGE 877
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.10 Channel n Interrupt Enable Set Name: Offset: Reset: Property: Bit 7 CHINTENSET 0x25 + n*0x08 [n=0..31] 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 EVD OVR RW RW 0 0 Bit 1 – EVD Channel Event Detected Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Event Detected Channel Interrupt Enable bit, which enables the Event Detected Channel interrupt.
PAGE 878
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.11 Channel n Interrupt Flag Status and Clear Name: Offset: Reset: Bit 7 CHINTFLAG 0x26 + n*0x08 [n=0..31] 0x00 6 5 4 3 Access 2 1 0 EVD OVR RW RW 0 0 Reset Bit 1 – EVD Channel Event Detected This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if CHINTENCLR/SET.EVD is '1'.
PAGE 879
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.12 Channel n Status Name: Offset: Reset: Bit 7 CHSTATUSn 0x27 + n*0x08 [n=0..31] 0x01 6 5 4 3 2 1 0 BUSYCH RDYUSR Access R R Reset 0 0 Bit 1 – BUSYCH Busy Channel This bit is cleared when channel is idle. This bit is set if an event on channel has not been handled by all event users connected to channel. When the event channel path is asynchronous, this bit is always read '0'.
PAGE 880
SAM D5x/E5x Family Data Sheet EVSYS – Event System 31.7.13 Event User m Name: Offset: Reset: Property: Bit USERm 0x0120 + m*0x04 [m=0..
PAGE 881
SAM D5x/E5x Family Data Sheet EVSYS – Event System ...........continued USERm User Multiplexer Description Path Type(1) m = 25..26 TCC1 EV0..1 TCC1 EVx A, S, R m = 27..30 TCC1 MC0..3 TCC1 MCx A, S, R m = 31..32 TCC2 EV0..1 TCC2 EVx A, S, R m = 33..35 TCC2 MC0..2 TCC2 MCx A, S, R m = 36..37 TCC3 EV0..1 TCC3 EVx A, S, R m = 38..39 TCC3 MC0..1 TCC3 MCx A, S, R m = 40..41 TCC4 EV0..1 TCC4 EVx A, S, R m = 42..43 TCC4 MC0..1 TCC4 MCx A, S, R m = 44..51 TC0..7 EVU TC0..
PAGE 882
SAM D5x/E5x Family Data Sheet EVSYS – Event System Value 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 other Description Channel 14 selected Channel 15 selected Channel 16 selected Channel 17 selected Channel 18 selected Channel 19 selected Channel 20 selected Channel 21 selected Channel 22 selected Channel 23 selected Channel 24 selected Channel 25 selected Channel 26 selected Channel 27 selected Channel 28 selected Channel 29 selected Channel 30 selected Channe
PAGE 883
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32. PORT - I/O Pin Controller 32.1 Overview The I/O Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups, collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and controlled individually or as a group. The number of PORT groups on a device may depend on the package or number of pins.
PAGE 884
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.3 Block Diagram Figure 32-1. PORT Block Diagram PORT Peripheral Mux Select Control Status Port Line Bundles IP Line Bundles PORTMUX and Pad Line Bundles I/O PADS Analog Pad Connections PERIPHERALS Digital Controls of Analog Blocks 32.4 ANALOG BLOCKS Signal Description Table 32-1.
PAGE 885
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller has control over the Output state of the pad, as well as the ability to read the current Physical Pad state. Refer to I/O Multiplexing and Considerations for details. Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be implemented. Related Links 6. I/O Multiplexing and Considerations 32.5.
PAGE 886
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.5.8 Register Access Protection All registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC). Note: Optional write protection is indicated by the "PAC Write Protection" property in the register description. Write protection does not apply for accesses through an external debugger. Related Links 27. PAC - Peripheral Access Controller 32.5.
PAGE 887
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller Figure 32-3. Overview of the peripheral functions multiplexing PORTMUX PORT bit y Port y PINCFG PMUXEN Port y Data+Config Port y PMUX[3:0] Port y Peripheral Mux Enable Port y Line Bundle 0 Port y PMUX Select Pad y PAD y Line Bundle Periph Signal 0 0 Periph Signal 1 1 1 Peripheral Signals to be muxed to Pad y Periph Signal 15 15 The I/O pins of the device are controlled by PORT peripheral registers.
PAGE 888
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.6.2.2 Operation Each I/O pin Pxy can be controlled by the registers in PORT. Each PORT group x has its own set of PORT registers, with a base address at byte address (PORT + 0x80 * group index) (A corresponds to group index 0, B to 1, etc...). Within that set of registers, the pin index is y, from 0 to 31. Refer to I/O Multiplexing and Considerations for details on available pin configuration and PORT groups.
PAGE 889
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller ...........continued DIR INEN PULLEN OUT Configuration 0 0 1 0 Pull-down; input disabled 0 0 1 1 Pull-up; input disabled 0 1 0 X Input 0 1 1 0 Input with pull-down 0 1 1 1 Input with pull-up 1 0 X X Output; input disabled 1 1 X X Output; input enabled 32.6.3.2 Input Configuration Figure 32-4.
PAGE 890
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller Figure 32-6. I/O Configuration - Totem-Pole Output with Disabled Input PULLEN PULLEN INEN DIR 0 0 1 DIR OUT IN INEN Figure 32-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN PULLEN INEN DIR 0 1 1 PULLEN INEN DIR 1 0 0 DIR OUT IN INEN Figure 32-8. I/O Configuration - Output with Pull PULLEN DIR OUT IN INEN 32.6.3.4 Digital Functionality Disabled Neither Input nor Output functionality are enabled. Figure 32-9.
PAGE 891
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller • Output (OUT): I/O pin will be set when the incoming event has a high level ('1') and cleared when the incoming event has a low-level ('0'). • Set (SET): I/O pin will be set when an incoming event is detected. • Clear (CLR): I/O pin will be cleared when an incoming event is detected. • Toggle (TGL): I/O pin will toggle when an incoming event is detected. The event is output to pin without any internal latency.
PAGE 892
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.7 Register Summary The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
PAGE 893
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller ...........continued Offset 0x24 0x28 0x2C 0x30 Name CTRL WRCONFIG EVCTRL Bit Pos.
PAGE 894
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.1 Data Direction Name: Offset: Reset: Property: DIR 0x00 0x00000000 PAC Write-Protection This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers.
PAGE 895
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.2 Data Direction Clear Name: Offset: Reset: Property: DIRCLR 0x04 0x00000000 PAC Write-Protection This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins.
PAGE 896
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.3 Data Direction Set Name: Offset: Reset: Property: DIRSET 0x08 0x00000000 PAC Write-Protection This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins.
PAGE 897
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.4 Data Direction Toggle Name: Offset: Reset: Property: DIRTGL 0x0C 0x00000000 PAC Write-Protection This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modifywrite operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction Clear (DIRCLR) registers.
PAGE 898
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.5 Data Output Value Name: Offset: Reset: Property: OUT 0x10 0x00000000 PAC Write-Protection This register sets the data output drive value for the individual I/O pins in the PORT. This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers.
PAGE 899
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.6 Data Output Value Clear Name: Offset: Reset: Property: OUTCLR 0x14 0x00000000 PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels low, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers.
PAGE 900
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.7 Data Output Value Set Name: Offset: Reset: Property: OUTSET 0x18 0x00000000 PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels high, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers.
PAGE 901
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.8 Data Output Value Toggle Name: Offset: Reset: Property: OUTTGL 0x1C 0x00000000 PAC Write-Protection This register allows the user to toggle the drive level of one or more output I/O pins, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers.
PAGE 902
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.9 Data Input Value Name: Offset: Reset: Property: IN 0x20 0x00000000 - Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 903
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.10 Control Name: Offset: Reset: Property: CTRL 0x24 0x00000000 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 904
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.11 Write Configuration Name: Offset: Reset: Property: WRCONFIG 0x28 0x00000000 PAC Write-Protection, Write-Only Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 905
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller Bit 30 – WRPINCFG Write PINCFG This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.
PAGE 906
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit. These bits will always read as zero. Value Description 0 The configuration of the corresponding I/O pin in the half-word group will be left unchanged. 1 The configuration of the corresponding I/O pin in the half-word PORT group will be updated. © 2019 Microchip Technology Inc.
PAGE 907
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.12 Event Input Control Name: Offset: Reset: Property: EVCTRL 0x2C 0x00000000 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 908
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller Table 32-4. PORT Event x Action ( x = [3..0] ) Value Name Description 0x0 OUT Output register of pin will be set to level of event. 0x1 SET Set output register of pin on event. 0x2 CLR Clear output register of pin on event. 0x3 TGL Toggle output register of pin on event. Table 32-5. PORT Event x Pin Identifier ( x = [3..0] ) Value Name Description 0x0 PIN0 Event action to be executed on PIN 0.
PAGE 909
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.13 Peripheral Multiplexing n Name: Offset: Reset: Property: PMUX 0x30 + n*0x01 [n=0..15] 0x00 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 910
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller ...........continued PMUXO[3:0] Name Description 0xD N Peripheral function N selected 0xE-0xF - Reserved Bits 3:0 – PMUXE[3:0] Peripheral Multiplexing for Even-Numbered Pin These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and Considerations.
PAGE 911
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller 32.8.14 Pin Configuration Name: Offset: Reset: Property: PINCFG 0x40 + n*0x01 [n=0..31] 0x00 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 912
SAM D5x/E5x Family Data Sheet PORT - I/O Pin Controller PMUXn is ignored. Writing '1' to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the Physical Pin state may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set. Value Description 0 The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive value.
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SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface 33. SERCOM – Serial Communication Interface 33.1 Overview There are up to eight instances of the Serial Communication interface (SERCOM) peripheral. A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode.
PAGE 914
SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface 33.3 Block Diagram Figure 33-1. SERCOM Block Diagram SERCOM Register Interface CONTROL/STATUS Mode Specific BAUD/ADDR TX/RX DATA Serial Engine Mode n Mode 1 Transmitter Baud Rate Generator Mode 0 Receiver 33.4 PAD[3:0] Address Match Signal Description See the respective SERCOM mode chapters for details. Related Links 34. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 35.
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SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface Related Links 18. PM – Power Manager 33.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock. The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a master.
PAGE 916
SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface • Data register (DATA) • Address register (ADDR) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger. Related Links 27. PAC - Peripheral Access Controller 33.5.9 Analog Connections Not applicable. 33.6 Functional Description 33.6.
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SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface 33.6.2 Basic Operation 33.6.2.1 Initialization The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register (CTRLA.MODE). Refer to table SERCOM Modes for details. Table 33-1. SERCOM Modes CTRLA.
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SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface Figure 33-3. Baud Rate Generator Selectable Internal Clk (GCLK) Baud Rate Generator 1 Ext Clk fref 0 Base Period /2 /1 CTRLA.MODE[0] /8 /2 /16 0 Tx Clk 1 1 CTRLA.MODE 0 1 Clock Recovery Rx Clk 0 Table 33-2 contains equations for the baud rate (in bits per second) and the BAUD register value for each operating mode.
PAGE 919
SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface where • D represent the data bits per frame • S represent the sum of start and first stop bits, if present. Table 33-3 shows the BAUD register value versus baud frequency fBAUD at a serial engine frequency of 48 MHz. This assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits). Table 33-3. BAUD Register Value vs. Baud Frequency 33.6.
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SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface Figure 33-5. Two Unique Addresses ADDR == Match rx shift register == ADDRMASK 33.6.3.1.3 Address Range The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. Figure 33-6. Address Range ADDRMASK 33.6.
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SAM D5x/E5x Family Data Sheet SERCOM – Serial Communication Interface 33.6.6 Events Not applicable. 33.6.7 Sleep Mode Operation The peripheral can operate in any Sleep mode where the selected serial clock is running. This clock can be external or generated by the internal baud-rate generator. The SERCOM interrupts can be used to wake-up the device from Sleep modes. Refer to the different SERCOM mode chapters for details. 33.6.
PAGE 922
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter 34.1 Overview The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). The USART uses the SERCOM transmitter and receiver, see 34.3 Block Diagram. Labels in uppercase letters are synchronous to CLK_SERCOMx_APB and accessible for CPU.
PAGE 923
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... • Can work with DMA • 32-bit Extension for Better System Bus Utilization Related Links 33.2 Features 34.3 Block Diagram Figure 34-1. USART Block Diagram BAUD GCLK (internal) TX DATA Baud Rate Generator /1 - /2 - /16 CTRLA.MODE TX Shift Register TxD RX Shift Register RxD XCK CTRLA.MODE 34.4 Status RX Buffer STATUS RX DATA Signal Description Table 34-1.
PAGE 924
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Table 34-2. USART Pin Configuration Pin Pin Configuration TxD Output RxD Input XCK Output or input The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in Table 34-2. Related Links 32. PORT - I/O Pin Controller 34.5.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 10.2 Nested Vector Interrupt Controller 34.5.6 Events Not applicable. 34.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... follow immediately, or the communication line can return to the Idle (high) state. The figure below illustrates the possible frame formats. Brackets denote optional bits. Figure 34-2. Frame Formats Frame (IDLE) St St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] [St/IDL] Start bit. Signal is always low. n, [n] [P] Data bits. 0 to [5..9] Parity bit. Either odd or even. Sp, [Sp] Stop bit. Signal is always high.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 7.2. Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity. 8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE). 9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate. 10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the CTRLB register (CTRLB.
PAGE 928
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the TxD pin. The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling, and which is used for TxD change: When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling edge of XCK. When CTRLA.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.6.2.6 Data Reception The receiver accepts data when a valid Start bit is detected. Each bit following the Start bit will be sampled according to the baud rate or XCK clock, and shifted into the receive Shift register until the first Stop bit of a frame is received. The second Stop bit will be ignored by the receiver.
PAGE 930
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Table 34-3. Asynchronous Receiver Error for 16-fold Oversampling D RSLOW [%] RFAST [%] Max. total error [%] Recommended max. Rx error [%] (Data bits+Parity) 5 94.12 107.69 +5.88/-7.69 ±2.5 6 94.92 106.67 +5.08/-6.67 ±2.0 7 95.52 105.88 +4.48/-5.88 ±2.0 8 96.00 105.26 +4.00/-5.26 ±2.0 9 96.39 104.76 +3.61/-4.76 ±1.5 10 96.70 104.35 +3.30/-4.35 ±1.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Figure 34-6. USART Rx Error Calculation Example SERCOM Receiver error acceptance sampling = x16 data bits = 10 parity = 0 start bit = stop bit = 1 + No baud generator offset error Accepted Receiver Error + + Fbaud(2Mbps) = 32MHz *1(BAUD=0) /16 Transmitter Error* Error Max 3.3% Error Max 3.3% Error Max 3.0% Baud Rate 2Mbps Error Min -4.05% Error Min -4.35% Error Min -4.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to CTRLB.RXEN will set/clear the RTS pin after a synchronization delay.
PAGE 933
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... minimum pulse width required. In this case the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is rejected since it does not meet the minimum requirement of 2/16 baud clock. Figure 34-11. IrDA Receive Decoding 0 Baud clock 0.5 1.5 1 2 2.5 IrDA encoded RXD RXD 20 SE clock cycles 34.6.3.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Figure 34-13. LIN Frame Format TxD Header Break Sync ID Slave response 1-8 Data bytes RxD Checksum Using the LIN command field (CTRLB.LINCMD), the complete header can be automatically transmitted, or software can control transmission of the various header components. When CTRLB.LINCMD=0x1, software controls transmission of the LIN header. In this case, software uses the following sequence. • CTRLB.LINCMD is written to 0x1.
PAGE 935
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Figure 34-15. RS485 Bus Connection USART RXD Differential Bus TXD TE The TE pin will remain high for the complete frame including stop bit(s). If a Guard Time is programmed in the Control C register (CTRLC.GTIME), the line will remain driven after the last character completion. The following figure shows a transfer with one stop bit and CTRLC.GTIME=3. Figure 34-16.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Protocol T=0 In T=0 protocol, a character is made up of: • one start bit, • eight data bits, • one parity bit • and one guard time, which lasts two bit times. The transfer is synchronous (CTRLA.CMODE=1). The transmitter shifts out the bits and does not drive the I/O line during the guard time. Additional guard time can be added by programming the Guard Time (CTRLC.GTIME).
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... When the USART repetition number reaches the programmed value in CTRLC.MAXITER, the STATUS.ITER bit is set and the internal iteration counter is reset. If the repetition of the character is acknowledged by the receiver before the maximum iteration is reached, the repetitions are stopped and the iteration counter is cleared.
PAGE 938
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 1. 2. 3. 4. 5. Abort the current transfer. Flush the transmit buffer. Disable transmitter (CTRLB.TXEN=0) – This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. – After disabling, the TxD pin will be tri-stated. Set the Collision Detected bit (STATUS.COLL) along with the Error Interrupt Flag (INTFLAG.ERROR).
PAGE 939
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... The figure below shows the order of transmit and receive when using 32-bit extension. Bytes are transmitted or received, and stored in order from 0 to 3. Only 8-bit and smaller character sizes are supported. If the character size is less than 8 bits, characters will still be 8-bit aligned within the 32-bit APB write or read. The unused bits within each byte will be zero for received data and unused for transmit data. Figure 34-22.
PAGE 940
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.6.4 DMA, Interrupts and Events Table 34-4.
PAGE 941
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Related Links 10.2 Nested Vector Interrupt Controller 34.6.4.3 Events Not applicable. 34.6.5 Sleep Mode Operation The behavior in Sleep mode is depending on the clock source and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY): • Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all Sleep modes. Any interrupt can wake-up the device. • External clocking, CTRLA.
PAGE 942
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.7 Offset Register Summary Name Bit Pos.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... ...........continued Offset Name Bit Pos. 0x2C ... Reserved 0x2F 0x30 34.8 DBGCTRL 7:0 DBGSTOP Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written.
PAGE 944
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.
PAGE 945
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Value 1 Description Synchronous communication. Bits 27:24 – FORM[3:0] Frame Format These bits define the frame format. These bits are not synchronized. FORM[3:0] Description 0x0 USART frame 0x1 USART frame with parity 0x2 LIN Master - Break and sync generation. See LIN Command (CTRLB.LINCMD). 0x3 Reserved 0x4 Auto-baud (LIN Slave) - break detection and auto-baud.
PAGE 946
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS/TE CTS 0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A 0x1 Reserved 0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3] 0x3 SERCOM_PAD[0] SERCOM_PAD[1] SERCOM_PAD[2] N/A Bits 15:13 – SAMPR[2:0] Sample Rate These bits select the sample rate. These bits are not synchronized. SAMPR[2:0] Description 0x0 16x over-sampling using arithmetic baud rate generation.
PAGE 947
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Bit 7 – RUNSTDBY Run In Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. RUNSTDBY External Clock Internal Clock 0x0 External clock is disconnected when ongoing transfer is finished. All reception is dropped. Generic clock is disabled when ongoing transfer is finished.
PAGE 948
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.
PAGE 949
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Value 0 1 Description The receiver is disabled or being enabled. The receiver is enabled or will be enabled when the USART is enabled. Bit 16 – TXEN Transmitter Enable Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately.
PAGE 950
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... ...........continued SFDE INTENSET.RXS INTENSET.RXC Description 1 1 1 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. Bit 8 – COLDEN Collision Detection Enable This bit enables collision detection. This bit is not synchronized. Value Description 0 Collision detection is not enabled. 1 Collision detection is enabled.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.
PAGE 952
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Value 0 1 Description NACK is sent on the ISO line for every parity error received. Successive parity errors are counted up to the value specified in CTRLC.MAXITER. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. Bit 16 – INACK Inhibit Not Acknowledge This bit controls whether a NACK is transmitted when a parity error is received.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.4 Baud Name: Offset: Reset: Property: Bit BAUD 0x0C 0x0000 Enable-Protected, PAC Write-Protection 15 14 13 12 11 10 9 8 R/W R/W R/W R/W Reset 0 0 R/W R/W R/W R/W 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[15:8] Access BAUD[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – BAUD[15:0] Baud Value Arithmetic Baud Rate Generation (CTRLA.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.5 Receive Pulse Length Register Name: Offset: Reset: Property: Bit RXPL 0x0E 0x00 Enable-Protected, PAC Write-Protection 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 RXPL[7:0] Access Reset Bits 7:0 – RXPL[7:0] Receive Pulse Length When the encoding format is set to IrDA (CTRLB.
PAGE 955
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.6 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 956
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled.
PAGE 957
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.7 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 958
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Value Description 0 Transmit Complete interrupt is disabled. 1 Transmit Complete interrupt is enabled.
PAGE 959
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.8 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit Access Reset 7 INTFLAG 0x18 0x00 - 6 5 4 3 2 1 0 ERROR RXBRK CTSIC RXS RXC TXC DRE R/W R/W R/W R/W R R/W R 0 0 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register.
PAGE 960
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready to be written. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.9 Status Name: Offset: Reset: Property: Bit STATUS 0x1A 0x0000 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ITER TXE COLL ISF CTS BUFOVF FERR PERR R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset Bit Access Reset Bit 7 – ITER Maximum Number of Repetitions Reached This bit is set when the maximum number of NACK repetitions or retransmissions is met in ISO7816 T=0 mode.
PAGE 962
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected.
PAGE 963
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... Bit 1 – ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value Description 0 Enable synchronization is not busy. 1 Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization.
PAGE 965
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.11 Receive Error Count Name: Offset: Reset: Property: RXERRCNT 0x20 0x00 Read-Synchronized Bit 7 6 5 4 Access R R R R Reset 0 0 0 0 3 2 1 0 R R R R 0 0 0 0 RXERRCNT[7:0] Bits 7:0 – RXERRCNT[7:0] Receive Error Count This register records the total number of parity errors and NACK errors combined in ISO7816 mode (CTRLA.FORM=0x7). This register is automatically cleared on read.
PAGE 966
SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.
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SAM D5x/E5x Family Data Sheet SERCOM USART - SERCOM Synchronous and Asyn... 34.8.14 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x30 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
PAGE 969
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35. 35.1 SERCOM SPI – SERCOM Serial Peripheral Interface Overview The Serial Peripheral Interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). The SPI uses the SERCOM transmitter and receiver configured as shown in 35.3 Block Diagram. Each side, master and slave, depicts a separate SPI containing a Shift register, a transmit buffer and a twolevel receive buffer.
PAGE 970
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.3 Block Diagram Figure 35-1. Full-Duplex SPI Master Slave Interconnection Master BAUD Slave Tx DATA Tx DATA ADDR/ADDRMASK SCK _SS baud rate generator shift register MISO shift register MOSI 35.4 rx buffer rx buffer Rx DATA Rx DATA == Address Match Signal Description Table 35-1.
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above. Related Links 32. PORT - I/O Pin Controller 35.5.2 Power Management This peripheral can continue to operate in any Sleep mode where its source clock is running. The interrupts can wake-up the device from Sleep modes.
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.5.8 Register Access Protection Registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC). PAC write protection is not available for the following registers: • Interrupt Flag Clear and Status register (INTFLAG) • Status register (STATUS) • Data register (DATA) Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description.
PAGE 973
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.6.2 Basic Operation 35.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRL.ENABLE=0): • • • • Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) Control B register (CTRLB), except Receiver Enable (CTRLB.
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK pin. This clock is used to clock the SPI Shift register. Related Links 33.6.2.3 Clock Generation – Baud-Rate Generator 35.6.2.4 Data Register The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address, referred to as the SPI Data register (DATA).
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface Figure 35-3.
PAGE 976
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA.
PAGE 977
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.6.3 Additional Features 35.6.3.1 Address Recognition When the SPI is configured for slave operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address match. If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.
PAGE 978
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface slaves, an SPI master can use general purpose I/O pins to control the SS line to each of the slaves on the bus, as shown in Multiple Slaves in Parallel. In this configuration, the single selected SPI slave will drive the tri-state MISO line. Figure 35-5.
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface Figure 35-7. Hardware Controlled SS T T T T T _SS SCK T = 1 to 2 baud cycles When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO. 35.6.3.6 Slave Select Low Detection In Slave mode, the SPI can wake the CPU when the slave select (SS) goes low. When the Slave Select Low Detect is enabled (CTRLB.SSDE=1), a high-to-low transition will set the Slave Select Low Interrupt flag (INTFLAG.
PAGE 980
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface loaded into the FIFO as Byte zero and data begins with Byte 1. INTFLAGS.RXC will then be raised for every 4 Bytes transferred. For transmit, there is a 32-bit holding buffer in the core domain. Once DATA has been registered in the core domain, INTFLAG.DRE will be raised, so that the next 32 bits can be written to the DATA register. Figure 35-10.
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.6.4 DMA, Interrupts, and Events Table 35-4. Module Request for SERCOM SPI Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes Slave Select low (SSL) NA Yes Error (ERROR) NA Yes 35.6.4.
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.6.5 Sleep Mode Operation The behavior in Sleep mode is depending on the master/slave configuration and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY): • Master operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will continue to run in Idle Sleep mode and in Standby Sleep mode. Any interrupt can wake-up the device. • Master operation, CTRLA.
PAGE 983
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.7 Offset Register Summary Name Bit Pos. 7:0 0x00 0x04 CTRLA CTRLB RUNSTDBY MODE[2:0] ENABLE 15:8 SWRST IBON 23:16 DIPO[1:0] 31:24 DORD 7:0 PLOADEN 15:8 AMODE[1:0] CPOL DOPO[1:0] CPHA FORM[3:0] CHSIZE[2:0] MSSEN SSDE 23:16 RXEN 31:24 7:0 0x08 CTRLC 0x0C BAUD ICSPACE[5:0] 15:8 23:16 31:24 DATA32B 7:0 BAUD[7:0] 0x0D ...
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SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface ...........continued Offset Name Bit Pos. 0x2C ... Reserved 0x2F 0x30 35.8 DBGCTRL 7:0 DBGSTOP Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written.
PAGE 985
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.
PAGE 986
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface Mode CPOL CPHA Leading Edge Trailing Edge 0x0 0 0 Rising, sample Falling, change 0x1 0 1 Rising, change Falling, sample 0x2 1 0 Falling, sample Rising, change 0x3 1 1 Falling, change Rising, sample Value 0 1 Description The data is sampled on a leading SCK edge and changed on a trailing SCK edge. The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
PAGE 987
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface ...........continued DOPO DO SCK Slave SS Master SS 0x1 Reserved 0x2 PAD[3] PAD[1] PAD[2] 0x3 Reserved PAD[2] Master SS pin when MSSEN = 1 otherwise System configuration Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the Buffer Overflow Status bit (STATUS.BUFOVF) is set when a buffer overflow occurs. This bit is not synchronized. Value Description 0 STATUS.
PAGE 988
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded. Any register write access during the ongoing Reset will result in an APB error. Reading any register will return the Reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.
PAGE 989
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.
PAGE 990
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface ...........continued AMODE[1:0] Name Description 0x2 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit 0x3 - Reserved Bit 13 – MSSEN Master Slave Select Enable This bit enables hardware Slave Select (SS) control. Value Description 0 Hardware SS control is disabled. 1 Hardware SS control is enabled.
PAGE 991
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.
PAGE 992
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.4 Baud Rate Name: Offset: Reset: Property: Bit BAUD 0x0C 0x00 PAC Write-Protection, Enable-Protected 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 BAUD[7:0] Access Reset Bits 7:0 – BAUD[7:0] Baud Register These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator. Related Links 33.6.2.
PAGE 993
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.5 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 994
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. © 2019 Microchip Technology Inc.
PAGE 995
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.6 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 996
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. © 2019 Microchip Technology Inc.
PAGE 997
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.7 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit Access Reset 7 INTFLAG 0x18 0x00 - 6 5 4 3 2 1 0 ERROR SSL RXC TXC DRE R/W R/W R R/W R 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding Status flags in the STATUS register.
PAGE 998
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.8 Status Name: Offset: Reset: Property: Bit 15 STATUS 0x1A 0x0000 – 14 13 12 11 10 9 8 2 1 0 LENERR Access R/W Reset Bit 0 7 6 5 4 3 BUFOVF Access R/W Reset 0 Bit 11 – LENERR Transaction Length Error This bit is set in slave mode when the length counter is enabled (LENGTH.LENEN=1) and the transfer length while SS is low is not a multiple of LENGTH.LEN. Writing '0' to this bit has no effect.
PAGE 999
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.9 Synchronization Busy Name: Offset: Reset: Property: Bit SYNCBUSY 0x1C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Access Reset Bit Access Reset Bit Access Reset Bit 2 1 0 LENGTH CTRLB ENABLE SWRST Access R R R R Reset 0 0 0 0 Bit 4 – LENGTH LENGTH Synchronization Busy Writing to the LENGTH register requires synchronization.
PAGE 1000
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface Value 0 1 Description Enable synchronization is not busy. Enable synchronization is busy. Bit 0 – SWRST Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.SWRST=1 until synchronization is complete. Value Description 0 SWRST synchronization is not busy. 1 SWRST synchronization is busy. © 2019 Microchip Technology Inc.
PAGE 1001
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.10 Length Name: Offset: Reset: Property: Bit 15 LENGTH 0x22 0x0000 PAC Write-Protection, Write-Synchronized 14 13 12 11 10 9 8 LENEN Access R/W Reset Bit 0 7 6 5 4 3 2 1 0 LEN[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 8 – LENEN Data Length Enable In 32-bit Extension mode, this bit field enables the length counter.
PAGE 1002
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.
PAGE 1003
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.
PAGE 1004
SAM D5x/E5x Family Data Sheet SERCOM SPI – SERCOM Serial Peripheral Interface 35.8.13 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x30 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
PAGE 1005
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36. SERCOM I2C – Inter-Integrated Circuit 36.1 Overview The Inter-Integrated Circuit (I2C) interface is one of the available modes in the Serial Communication Interface (SERCOM). The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 36-1. Labels in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM.
PAGE 1006
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.3 Block Diagram Figure 36-1. I2C Single-Master Single-Slave Interconnection Master BAUD TxDATA TxDATA 0 baud rate generator Slave SCL SCL hold low 0 SCL hold low shift register shift register 0 SDA RxDATA 36.
PAGE 1007
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.5.2 Power Management This peripheral can continue to operate in any Sleep mode where its source clock is running. The interrupts can wake-up the device from Sleep modes. Related Links 18. PM – Power Manager 36.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock.
PAGE 1008
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit PAC write protection is not available for the following registers: • • • • Interrupt Flag Clear and Status register (INTFLAG) Status register (STATUS) Data register (DATA) Address register (ADDR) Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links 27.
PAGE 1009
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Figure 36-2. Transaction Diagram Symbols Bus Driver Special Bus Conditions Master driving bus S START condition Slave driving bus Sr repeated START condition Either Master or Slave driving bus P STOP condition Data Package Direction Acknowledge Master Read R Acknowledge (ACK) A '0' '1' W A Master Write Not Acknowledge (NACK) '1' '0' Figure 36-3. Basic I2C Transaction Diagram SDA SCL 6..
PAGE 1010
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the I2C is enabled it must be configured as outlined by the following steps: 1. Select I2C Master or Slave mode by writing 0x4 (Slave mode) or 0x5 (Master mode) to the Operating Mode bits in the CTRLA register (CTRLA.MODE). 2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD). 3.
PAGE 1011
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Figure 36-4. Bus State Diagram RESET UNKNOWN (0b00) Timeout or Stop Condition Start Condition IDLE (0b01) Timeout or Stop Condition BUSY (0b11) Write ADDR to generate Start Condition OWNER (0b10) Lost Arbitration Repeated Start Condition Stop Condition Write ADDR to generate Repeated Start Condition The Bus state machine is active when the I2C master is enabled.
PAGE 1012
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.6.2.4 I2C Master Operation The I2C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering of operations, and a Special Smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN). The I2C master has two interrupt strategies.
PAGE 1013
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Figure 36-6. I2C Master Behavioral Diagram (SCLSM=1) APPLICATION Master Bus INTERRUPT + SCL HOLD M1 M2 BUSY P M3 IDLE S M4 ADDRESS Wait for IDLE SW R/W BUSY SW R/W A SW P SW Sr W A M1 BUSY M2 IDLE M3 BUSY DATA SW A/A Slave Bus INTERRUPT + SCL HOLD SW Software interaction SW BUSY The master provides data on the bus P IDLE M4 M2 Addressed slave provides data on the bus Sr R A M3 DATA A/A 36.6.2.4.
PAGE 1014
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Figure 36-7. SCL Timing TRISE P S Sr TLOW SCL THIGH TFALL TBUF SDA TSU;STO THD;STA TSU;STA The following parameters are timed using the SCL low time period TLOW. This comes from the Master Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.
PAGE 1015
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be nonzero. Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA register is written in smart mode.
PAGE 1016
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit The missing ACK response can indicate that the I2C slave is busy with other tasks or sleeping. Therefore, it is not able to respond. In this event, the next step can be either issuing a Stop condition (recommended) or resending the address packet by a repeated Start condition. When using SMBus logic, the slave must ACK the address. If there is no response, it means that the slave is not available on the bus.
PAGE 1017
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.6.2.4.4 Receiving Data Packets (SCLSM=0) When INTFLAG.SB is set, the I2C master will already have received one data packet. The I2C master must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration.
PAGE 1018
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Figure 36-9. 10-bit Address Transmission for a Read Transaction MB INTERRUPT 1 S 11110 addr[9:8] W A S W A addr[7:0] Sr 11110 addr[9:8] R A This implies the following procedure for a 10-bit read operation: 1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit (ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR). 2.
PAGE 1019
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in Slave Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging. For master reads, an address and data interrupt will be issued simultaneously after the address acknowledge.
PAGE 1020
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Case 1: Address packet accepted – Read flag set The STATUS.DIR bit is ‘1’, indicating an I2C master read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C slave hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C slave will wait for a new Start condition and address match.
PAGE 1021
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C slave will send an acknowledge according to CTRLB.ACKACT. Case 1: Data received INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction. Case 2: Data sent When a byte transmission is successfully completed, the INTFLAG.DRDY Interrupt flag is set. If NACK is received, indicated by STATUS.
PAGE 1022
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Figure 36-13. PMBus Group Command Example Command/Data S ADDRESS 0 W A n Bytes A AMATCH INTERRUPT DRDY INTERRUPT Command/Data Sr ADDRESS 1 (this slave) S W W A 36.6.3 ADDRESS 2 W A n Bytes A PREC INTERRUPT Command/Data Sr S W n Bytes A P S W Additional Features 36.6.3.
PAGE 1023
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Figure 36-14. I2C Pad Interface SCL_OUT/ SDA_OUT SCL_OUT/ SDA_OUT pad PINOUT I2C Driver SCL/SDA pad SCL_IN/ SDA_IN PINOUT 36.6.3.4 Quick Command Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding Interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after the slave acknowledges the address.
PAGE 1024
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit after a Master Code is received. In this case, no Length Error (STATUS.LENERR) is registered, regardless of the LENGTH.LENEN setting. When SCL clock stretch mode is selected (CTRLA.SCLSM=1) and the transaction is a master write, the selected Acknowledge Action (CTRLB.ACKACT) will only be used to ACK/NACK each 4th byte. All other bytes are ACKed. This allows the user to write CTRLB.
PAGE 1025
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Table 36-1. Module Request for SERCOM I2C Slave Condition Request DMA Interrupt Data needed for transmit (TX) (Slave Transmit mode) Yes (request cleared when data is written) Data received (RX) (Slave Receive mode) Yes (request cleared when data is read) Event NA Data Ready (DRDY) Yes Address Match (AMATCH) Yes Stop received (PREC) Yes Error (ERROR) Yes Table 36-2.
PAGE 1026
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit • Read data needed for transmit (TX): The request is set when data is needed for a master read operation. The request is cleared when DATA is written. 36.6.4.1.2 Master DMA When using the I2C master with DMA, the ADDR register must be written with the desired address (ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.
PAGE 1027
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.6.5 Sleep Mode Operation I2C Master Operation The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in Standby Sleep mode. Any interrupt can wake-up the device. If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished. Any interrupt can wake-up the device.
PAGE 1028
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.7 Offset Register Summary - I2C Slave Name Bit Pos. 7:0 0x00 CTRLA RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN 31:24 SDAHOLD[1:0] PINOUT LOWTOUT SCLSM SPEED[1:0] 7:0 0x04 CTRLB 15:8 AMODE[1:0] AACKEN 23:16 GCMD ACKACT SMEN CMD[1:0] 31:24 7:0 0x08 CTRLC SDASETUP[3:0] 15:8 23:16 31:24 DATA32B 0x0C ...
PAGE 1029
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8 Register Description - I2C Slave Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
PAGE 1030
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.
PAGE 1031
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Value 0x2 0x3 Description High-speed mode (Hs-mode) up to 3.4 MHz Reserved Bit 23 – SEXTTOEN Slave SCL Low Extend Time-Out This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set.
PAGE 1032
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Value 1 Description The peripheral is enabled. Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
PAGE 1033
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.
PAGE 1034
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit ...........
PAGE 1035
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Bit 8 – SMEN Smart Mode Enable When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read. This bit is not write-synchronized. Value Description 0 Smart mode is disabled. 1 Smart mode is enabled. Related Links 33. SERCOM – Serial Communication Interface © 2019 Microchip Technology Inc.
PAGE 1036
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.
PAGE 1037
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 1038
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 1039
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit Access Reset 7 INTFLAG 0x18 0x00 - 6 5 4 3 2 1 0 ERROR DRDY AMATCH PREC R/W R/W R/W R/W 0 0 0 0 Bit 7 – ERROR Error This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The corresponding bits in STATUS are LENERR, SEXTTOUT, LOWTOUT, COLL, and BUSERR.
PAGE 1040
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.7 Status Name: Offset: Reset: Property: Bit 15 STATUS 0x1A 0x0000 - 14 13 12 11 Access Reset Bit 5 10 9 HS SEXTTOUT R/W R/W 0 0 8 7 6 4 3 2 1 0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR Access R R/W R R R R/W R/W Reset 0 0 0 0 0 0 0 Bit 10 – HS High-speed This bit is set if the slave detects a START followed by a Master Code transmission. Writing a '0' to this bit has no effect.
PAGE 1041
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Bit 4 – SR Repeated Start When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition. This flag is only valid while the INTFLAG.AMATCH flag is one. Value Description 0 Start condition on last address match 1 Repeated start condition on last address match Bit 3 – DIR Read / Write Direction The Read/Write Direction (STATUS.
PAGE 1042
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.8 Synchronization Busy Name: Offset: Reset: Property: Bit SYNCBUSY 0x1C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Access Reset Bit Access Reset Bit Access Reset Bit 1 0 LENGTH ENABLE SWRST Access R R R Reset 0 0 0 Bit 4 – LENGTH LENGTH Synchronization Busy Writing LENGTH requires synchronization.
PAGE 1043
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Value 1 Description SWRST synchronization is busy. © 2019 Microchip Technology Inc.
PAGE 1044
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.9 Length Name: Offset: Reset: Property: Bit 15 LENGTH 0x22 0x0000 PAC Write-Protection, Write-Synchronized 14 13 12 11 10 9 8 LENEN Access R/W Reset Bit 0 7 6 5 4 3 2 1 0 LEN[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 8 – LENEN Data Length Enable In 32-bit Extension mode (CTRLC.DATA32B=1), this bit field enables the length counter.
PAGE 1045
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.
PAGE 1046
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.8.
PAGE 1047
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.9 Offset Register Summary - I2C Master Name Bit Pos. 7:0 0x00 CTRLA RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN 31:24 MEXTTOEN SDAHOLD[1:0] LOWTOUT INACTOUT[1:0] PINOUT SCLSM SPEED[1:0] 7:0 0x04 CTRLB 15:8 QCEN 23:16 ACKACT SMEN CMD[1:0] 31:24 7:0 0x08 CTRLC 15:8 23:16 31:24 0x0C BAUD DATA32B 7:0 BAUD[7:0] 15:8 BAUDLOW[7:0] 23:16 HSBAUD[7:0] 31:24 HSBAUDLOW[7:0] 0x10 ...
PAGE 1048
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit ...........continued Offset Name Bit Pos. 0x2C ... Reserved 0x2F 0x30 36.10 DBGCTRL 7:0 DBGSTOP Register Description - I2C Master Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
PAGE 1049
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.
PAGE 1050
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Value 0x3 Name 205US Description 20-21 SCL cycle time-out (200-210µs) Bit 27 – SCLSM SCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value Description 0 SCL stretch according to Figure 36-5. 1 SCL stretch only after ACK bit, Figure 36-6. Bits 25:24 – SPEED[1:0] Transfer Speed These bits define bus speed. These bits are not synchronized.
PAGE 1051
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Bit 16 – PINOUT Pin Usage This bit set the pin usage to either two- or four-wire operation: This bit is not synchronized. Value Description 0 4-wire operation disabled. 1 4-wire operation enabled. Bit 7 – RUNSTDBY Run in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value Description 0 GCLK_SERCOMx_CORE is disabled and the I2C master will not operate in standby sleep mode.
PAGE 1052
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.
PAGE 1053
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP). Table 36-4.
PAGE 1054
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.3 Control C Name: Offset: Reset: Property: Bit 31 CTRLC 0x08 0x00000000 PAC Write-Protection, Enable-Protected 30 29 28 27 26 25 24 DATA32B Access R/W Reset Bit 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit 24 – DATA32B Data 32 Bit This bit enables 32-bit data writes and reads to/from the DATA register.
PAGE 1055
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.
PAGE 1056
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.5 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 1057
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.6 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 1058
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.7 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit Access Reset 7 INTFLAG 0x18 0x00 - 6 5 4 3 2 1 0 ERROR SB MB R/W R/W R/W 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS register.
PAGE 1059
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.
PAGE 1060
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Bit 6 – LOWTOUT SCL Low Time-Out This bit is set if an SCL low time-out occurs. Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bits 5:4 – BUSSTATE[1:0] Bus State These bits indicate the current I2C Bus state.
PAGE 1061
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.9 Synchronization Busy Name: Offset: Reset: Bit SYNCBUSY 0x1C 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Access Reset Bit Access Reset Bit Access Reset Bit 2 1 0 SYSOP ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – SYSOP System Operation Synchronization Busy Writing CTRLB.CMD, STATUS.
PAGE 1062
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.
PAGE 1063
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit Bits 10:0 – ADDR[10:0] Address When ADDR is written, the consecutive operation will depend on the bus state: UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated. BUSY: The I2C master will await further operation until the bus becomes IDLE. IDLE: The I2C master will issue a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low, and STATUS.
PAGE 1064
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.
PAGE 1065
SAM D5x/E5x Family Data Sheet SERCOM I2C – Inter-Integrated Circuit 36.10.12 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x30 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls functionality when the CPU is halted by an external debugger. Value Description 0 The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
PAGE 1066
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37. 37.1 QSPI - Quad Serial Peripheral Interface Overview The Quad SPI Interface (QSPI) circuit is a synchronous serial data link that provides communication with external devices in Master mode. The QSPI can be used in “SPI mode” to interface serial peripherals, such as ADCs, DACs, LCD controllers and sensors, or in “Serial Memory Mode” to interface serial Flash memories.
PAGE 1067
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.3 Block Diagram Figure 37-1. QSPI Block Diagram MCLK Peripheral Clock SCK QSPI Peripheral Bridge MOSI/DATA0 APB MISO/DATA1 CPU DATA2 AHB MATRIX DATA3 CS DMA Interrupt Control QSPI Interrupt 37.4 Signal Description Table 37-1.
PAGE 1068
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Related Links 32. PORT - I/O Pin Controller 37.5.2 Power Management The QSPI will continue to operate in any Sleep mode where the selected source clock is running. The QSPI interrupts can be used to wake up the device from sleep modes. Refer to the Power Manager chapter for details on the different sleep modes. 37.5.
PAGE 1069
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). Using the QSPI DMA requests requires the DMA Controller to be configured first. Note: DMAC write access must be 32-bit aligned. If a single byte is to be written in a 32-bit word, the rest of the word must be filled with 'ones'. Related Links 22. DMAC – Direct Memory Access Controller 37.5.
PAGE 1070
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.6.2 Basic Operation 37.6.2.1 Initialization After Power-On Reset, this peripheral is enabled . 37.6.2.2 Enabling, Disabling, and Resetting The peripheral is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The peripheral is disabled by writing a '0' to CTRLA.ENABLE. The peripheral is reset by writing a '1' to the Software Reset bit (CTRLA.SWRST). 37.6.
PAGE 1071
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Figure 37-3. QSPI Transfer Modes (BAUD.CPHA = 0, 8-bit transfer) SCK Cycle (for reference) 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB * CS (to slave) * Not defined, but normally MSB of previous character received Figure 37-4. QSPI Transfer Modes (BAUD.
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SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface consecutive transfers. In Serial Memory mode, this delay is not programmable and DLYBCT settings are ignored. • The delay before SCK is programmed by writing the Delay Before SCK bit field in the BAUD register (BAUD.DLYBS), allowing to delay the start of SPCK after the chip select has been asserted. These delays allow the QSPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 37-5.
PAGE 1073
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.6.7.2 SPI Mode Block Diagram Figure 37-6. SPI Mode Block Diagram BAUD BAUD Peripheral Clock Baud Rate Generator SCK Serial Clock BAUD RXDATA MISO RXC ERROR DATA CPHA CPOL LSB MSB Shift Register MOSI CTRLB DATALEN TXDATA DATA Chip Select Controller DRE CS CTRLB CSMODE © 2019 Microchip Technology Inc.
PAGE 1074
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.6.7.3 SPI Mode Flow Diagram Figure 37-7. SPI Mode Flow Diagram QSI Enable 1 DRE ? 0 CS = 0 Delay DLYBS Serializer = TXDATA DRE = 1 Data Transfer RXDATA = Serializer RXC = 1 Delay DLYBCT DRE ? 0 1 CS = 1 Delay DLYCS © 2019 Microchip Technology Inc.
PAGE 1075
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Figure 37-8. Interrupt Flags Behaviour 1 2 3 4 5 6 7 8 SCK CS MOSI (from master) MSB 6 5 4 3 2 1 LSB DRE RXDATA Read Write in TXDATA RXC MISO (from slave) MSB 6 5 4 3 2 1 LSB TXC Shift register empty 37.6.7.
PAGE 1076
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Depending on the application software handling the flags or servicing other interrupts or other tasks, the processor may not reload the TXDATA in time to keep the Chip Select active (low). A null Delay Between Consecutive Transfer bit field value in the CTRLB register (CTRLB.DLYBCT) will give even less time for the processor to reload the TXDATA.
PAGE 1077
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Figure 37-9. Instruction Frame CS SCK DATA0 A20 A16 A12 A8 A4 A0 O4 O0 D4 D0 D4 D0 DATA1 A21 A17 A13 A9 A5 A1 O5 O1 D5 D1 D5 D1 DATA2 A22 A18 A14 A10 A6 A2 O6 O2 D6 D2 D6 D2 A23 A19 A15 A11 A7 A3 O7 O3 D7 D3 DATA3 Instruction EBh Address D7 D3 Option Dummy cycles Data 37.6.8.
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SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface • OPTCODELEN field configures the option code length (0 -> 1-bit / 1 -> 2-bit / 2 -> 4-bit / 3 -> 8-bit). The value written in OPTCODELEN must be consistent with value written in the field WIDTH. For example: OPTCODELEN = 0 (1-bit option code) is not coherent with WIDTH = 6 (option code sent with QuadSPI protocol, thus the minimum length of the option code is 4-bit).
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SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Figure 37-10.
PAGE 1080
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.6.8.3 Read Memory Transfer The user can access the data of the serial memory by sending an instruction with DATAEN=1 and TFRTYP=0x1 in the Instruction Frame register (INSTRFRAME). In this mode the QSPI is able to read data at random address into the serial flash memory, allowing the CPU to execute code directly from it (XIP execute-in-place).
PAGE 1081
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Example 37-1. Example 1 Instruction in Single-bit SPI, without address, without option, without data. Command: CHIP ERASE (C7h). • Write 0x0000_00C7 to INSTRCTRL register. • Write 0x0000_0010 to INSTRFRAME register. • Wait for INTFLAG.INSTREND to rise. Figure 37-12. Instruction Transmission Waveform 1 Write INSTRFRAME CS SCK MOSI / DATA0 Instruction C7h INTFLAG.INSTREND Example 37-2.
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SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Figure 37-14. Instruction Transmission Waveform 3 Write INSTRADDR Write INSTRFRAME CS SCK A23 A22 A21 A20 MOSI / DATA0 Instruction 20h A3 A2 A1 A0 Address INTFLAG.INSTREND Example 37-4. Example 4 Instruction in Single-bit SPI, without address, without option, with data write in Single-bit SPI. Command: SET BURST (77h) • • • • Write 0x0000_0077 to INSTRCTRL register. Write 0x0000_2090 to INSTRFRAME register.
PAGE 1083
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface • Wait for INTFLAG.INSTREND to rise. Figure 37-16. Instruction Transmission Waveform 5 Write INSTRFRAME CS SCK DATA0 A22 A20 A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 D6 D4 D2 D0 DATA1 A23 A21 A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 D7 D5 D3 D1 D7 D5 D3 D1 Data Address Instruction 02h D6 D4 D2 D0 INTFLAG.INSTREND Write AHB Set CTRLA.LASTXFER Example 37-6.
PAGE 1084
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface • Read data from the QSPI system bus memory space (0x040 00000–0x0500_0000). Fetch is enabled, the address of the system bus read accesses is always used. • Write LASTXFR bit in CTRLA register to '1'. • Wait for INTFLAG.INSTREND to rise. Figure 37-18.
PAGE 1085
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface The scrambling and unscrambling are performed on-the-fly without impacting the throughput. The scrambling method depends on the user-configurable Scrambling User Key in the Scrambling Key register (SCRAMBKEY.KEY). This register is only accessible in write mode. By default, the scrambling and unscrambling algorithm includes the scrambling user key, plus a devicedependent random value.
PAGE 1086
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.7 Offset Register Summary Name Bit Pos.
PAGE 1087
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface ...........continued Offset Name Bit Pos. 7:0 0x34 INSTRCTRL INSTR[7:0] 15:8 23:16 OPTCODE[7:0] 31:24 0x38 INSTRFRAME 7:0 DATAEN OPTCODEEN 15:8 DDREN CRMODE ADDREN INSTREN TFRTYPE[1:0] WIDTH[2:0] ADDRLEN 23:16 OPTCODELEN[1:0] DUMMYLEN[4:0] 31:24 0x3C ... Reserved 0x3F 7:0 0x40 SCRAMBCTRL RANDOMDIS ENABLE 15:8 23:16 31:24 7:0 0x44 37.
PAGE 1088
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.1 Control A Name: Offset: Reset: Property: CTRLA 0x00 0x00000000 - Control A Bit 31 30 29 28 27 26 25 24 LASTXFER Access W Reset 0 Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE SWRST R/W W 0 0 Access Reset Bit Access Reset Bit Access Reset Bit 24 – LASTXFER Last Transfer 0: No effect.
PAGE 1089
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1090
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Value 0x4 0x5 0x6 0x7 0x8 0x9-0xF Name 12BITS 13BITS 14BITS 15BITS 16BITS Description 12-bits transfer 13-bits transfer 14-bits transfer 15-bits transfer 16-bits transfer Reserved Bits 5:4 – CSMODE[1:0] Chip Select Mode The CSMODE field determines how the chip select is de-asserted. Value Name Description 0x0 NORELOAD The chip select is de-asserted if TD has not been reloaded before the end of the current transfer.
PAGE 1091
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1092
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Value 0 1 Description Data is captured on the leading edge of SCK and changed on the following edge of SCK. Data is changed on the leading edge of SCK and captured on the following edge of SCK. Bit 0 – CPOL Clock Polarity CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices.
PAGE 1093
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1094
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1095
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1096
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Bit 2 – TXC Transmission Complete Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request. Value Description 0 The TXC interrupt is disabled. 1 The TXC interrupt is enabled. Bit 1 – DRE Transmit Data Register Empty Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request.
PAGE 1097
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1098
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Bit 2 – TXC Transmission Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request. Value Description 0 The TXC interrupt is disabled. 1 The TXC interrupt is enabled. Bit 1 – DRE Transmit Data Register Empty Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request.
PAGE 1099
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1100
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Bit 1 – DRE Transmit Data Register Empty 0: Data has been written to TXDATA and not yet transferred to the serializer. 1: The last data written in the TXDATA has been transferred to the serializer. This bit is '0' when the QSPI is disabled or at reset. The bit is set as soon as ENABLE bit is set. Bit 0 – RXC Receive Data Register Full 0: No data has been received since the last read of RXDATA.
PAGE 1101
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.9 Status Name: Offset: Reset: Property: Bit STATUS 0x20 0x00000200 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access Reset Bit Access Reset Bit CSSTATUS Access R Reset 1 Bit 7 6 5 4 3 2 1 0 ENABLE Access R Reset 0 Bit 9 – CSSTATUS Chip Select Value Description 0 Chip Select is asserted. 1 Chip Select is not asserted.
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SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1103
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1104
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1105
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Value 0x1 0x2 0x3 Name READMEMORY Description Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. WRITE Write transfer into the serial memory.Scrambling is not performed. WRITEMEMORY Write data transfer into the serial memory. If enabled, scrambling is performed.
PAGE 1106
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Name Description SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Singlebit SPI DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI DUAL_IO Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI QUAD_IO Instruction: Single-
PAGE 1107
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1108
SAM D5x/E5x Family Data Sheet QSPI - Quad Serial Peripheral Interface 37.8.
PAGE 1109
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38. USB – Universal Serial Bus 38.1 Overview The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification supporting both device and embedded host modes. The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 16 endpoints.
PAGE 1110
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus – – – – – 38.3 No pipe size limitations Supports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree Built-in DMA with multi-packet support and dual bank for all pipes Supports feedback endpoint Supports the USB 2.0 Phase-locked SOFs feature USB Block Diagram Figure 38-1.
PAGE 1111
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.5.1 I/O Lines The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to assign the USB pins to their peripheral functions. A 1kHz SOF clock is available on an external pin. The user must first configure the I/O Controller to assign the 1kHz SOF clock to the peripheral function. The SOF clock is available for device and host mode. 38.5.
PAGE 1112
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.5.6 Events Not applicable. 38.5.7 Debug Operation When the CPU is halted in debug mode the USB peripheral continues normal operation. If the USB peripheral is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 38.5.
PAGE 1113
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Figure 38-2. General States HW RESET | CTRLA.SWRST Any state Idle CTRLA.ENABLE = 1 CTRLA.MODE =0 CTRLA.ENABLE = 0 CTRLA.ENABLE = 1 CTRLA.MODE =1 CTRLA.ENABLE = 0 Device Host After a hardware reset, the USB is in the idle state. In this state: • • • • The module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset. The module clock is stopped in order to minimize power consumption. The USB pad is in suspend mode.
PAGE 1114
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Refer to 38.6.2 USB Device Operations for the basic operation of the device mode. Refer to 38.6.3 Host Operations for the basic operation of the host mode. 38.6.2 USB Device Operations This section gives an overview of the USB module device operation during normal transactions. For more details on general USB and USB protocol, refer to the Universal Serial Bus specification revision 2.1. 38.6.2.
PAGE 1115
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Figure 38-3. Multi-Packet Feature - Reduction of CPU Overhead Data Payload Without Multi-packet support Transfer Complete Interrupt & Data Processing Maximum Endpoint size With Multi-packet support 38.6.2.4 USB Reset The USB bus reset is initiated by a connected host and managed by hardware.
PAGE 1116
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus When the data PID matches and if the Received Setup Complete interrupt bit in the Device Endpoint Interrupt Flag register (EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device Endpoint Status register (EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the number of received data bytes exceeds the endpoint's maximum data payload size as specified by the PCKSIZE.
PAGE 1117
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet. When the endpoint is enabled, the USB module then checks the Endpoint Configuration register (EPCFG) of the addressed output endpoint. If the type of the endpoint (EPCFG.
PAGE 1118
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY management are as for normal operation. If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by PCKSIZE.SIZE after the transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the endpoint is not isochronous. If the updated PCKSIZE.BYTE_COUNT is equal to PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction), EPSTATUS.
PAGE 1119
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not isochronous, a NAK handshake is returned to the host. The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor. The data pointed to by the Data Buffer Address (ADDR) is sent to the host in a DATA0 packet if the endpoint is isochronous.
PAGE 1120
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Figure 38-6. Ping-Pong Overview Endpoint single bank Without Ping Pong t Endpoint dual bank Bank0 With Ping Pong t Bank1 USB data packet Available time for data processing by CPU to avoid NACK The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next transaction, and is updated after each transaction. According to EPSTATUS.CURBK, EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0 or EPINTFLAG.TRCPT1 or EPINTFLAG.
PAGE 1121
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Figure 38-7. Pad Behavior Idle CTRLA.ENABLE = 0 | CTRLB.DETACH = 1 | INTFLAG.SUSPEND = 1 CTRLA.ENABLE = 1 | CTRLB.DETACH = 0 | INTFLAG.SUSPEND = 0 Active In Idle state, the pad is in Low Power Consumption mode. In Active state, the pad is active. The following figure, Pad Events, illustrates the pad events leading to a PAD state change. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Figure 38-8. Pad Events Suspend detected Cleared on Wakeup Wakeup detected Active Idle Cleared by software to acknowledge the interrupt Active The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB Suspend state has been detected on the USB bus. The USB pad is then automatically put in the Idle state. The detection of a non-idle state sets the Wake Up Interrupt bit (INTFLAG.
PAGE 1123
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already started, the CTRLB.UPRSM is cleared and the upstream resume request is ignored. 38.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction.
PAGE 1124
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.6.2.16 USB Device Interrupt Figure 38-9. Device Interrupt EPINTFLAG7.STALL EPINTENSET7.STALL0/STALL1 EPINTFLAG7.TRFAIL1 EPINTENSET7.TRFAIL1 EPINTFLAG7.TRFAIL0 EPINTSMRY EPINTENSET7.TRFAIL0 ENDPOINT7 EPINTFLAG7.RXSTP EPINT7 EPINTENSET7.RXSTP EPINT6 EPINTFLAG7.TRCPT1 EPINTENSET7.TRCPT1 EPINTFLAG7.TRCPT0 EPINTENSET7.TRCPT0 USB EndPoint Interrupt EPINTFLAG0.STALL EPINTENSET0.STALL0/STALL1 EPINTFLAG0.TRFAIL1 EPINTENSET0.TRFAIL1 EPINTFLAG0.
PAGE 1125
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.6.3 Host Operations This section gives an overview of the USB module Host operation during normal transactions. For more details on general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1. 38.6.3.1 Device Detection and Disconnection Prior to device detection the software must set the VBUS is OK bit (CTRLB.VBUSOK) register when the VBUS is available. This notifies the USB host that USB operations can be started.
PAGE 1126
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus known values before using the pipe, so that the USB controller does not read the random values from the RAM. The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported by the device for the endpoint associated with this pipe. The Address of Data Buffer register (ADDR) should be set to the data buffer used for pipe transfers. The Pipe Bank bit (PCFG.BK) should be set to one if dual banking is desired.
PAGE 1127
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus suspend state by sending a Downstream Resume on the USB bus (CTRLB.RESUME set to 1). In both cases, when the downstream resume is completed, the CTRLB.SOFE bit is automatically set and the host enters again the active state. 38.6.3.8 Phase-locked SOFs To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained while the USB connection is not in the active state.
PAGE 1128
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by looking at Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN). When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only PINTFLAG.TRCPT0 and PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK is 1), both PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1 are used. 38.6.3.
PAGE 1129
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus stage if the USB detects a corrupted packet. The IN packet will remain stored in the bank and PINTFLAG.TRCPT0/1 will be set. 38.6.3.15 PERR Error This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is set. The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
PAGE 1130
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation. © 2019 Microchip Technology Inc.
PAGE 1131
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.6.3.17 Host Interrupt Figure 38-10. Host Interrupt PINTFLAG7.STALL PINTENSET.STALL PINTFLAG7.PERR PINTENSET.PERR PINTFLAG7.TRFAIL PINTENSET.TRFAIL PIPE7 PINTFLAG7.TXSTP PINTSMRY PINT7 PINTENSET.TXSTP PINT6 PINTFLAG7.TRCPT1 PINTENSET.TRCPT1 PINTFLAG7.TRCPT0 PINTENSET.TRCPT0 USB PIPE Interrupt PINTFLAG0.STALL PINTENSET.STALL PINTFLAG0.PERR PINTENSET.PERR PINTFLAG0.TRFAIL PINTENSET.TRFAIL PINTFLAG0.TXSTP PIPE0 PINT1 PINT0 PINTENSET.
PAGE 1132
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.7 Register Summary The register mapping depends on the Operating Mode field in the Control A register (CTRLA.MODE). The register summary is detailed below. 38.7.1 Offset Common Device Summary Name Bit Pos. 0x00 CTRLA 7:0 0x01 Reserved 0x02 SYNCBUSY 7:0 0x03 QOSCTRL 7:0 0x0D FSMSTATUS 7:0 MODE RUNSTBY DQOS[1:0] 7:0 DESCADD[7:0] 0x25 15:8 DESCADD[15:8] 23:16 DESCADD[23:16] DESCADD 0x27 31:24 0x28 7:0 0x29 38.7.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus ...........continued Offset 0x1C 0x1D Name INTFLAG 0x1E Reserved 0x1F Reserved 0x20 0x21 EPINTSMRY 0x22 Reserved 0x23 Reserved Bit Pos. 7:0 RAMACER UPRSM EORSM WAKEUP EORST SOF 15:8 SUSPEND LPMSUSP 7:0 EPINT[7:0] 15:8 EPINT[15:8] LPMNYET Table 38-2. Device Endpoint Register n Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Table 38-4. Device Endpoint n Descriptor Bank 1 Offset 0x Name Bit Pos. n0 + 0x10 + index 0x00 7:0 ADD[7:0] 0x01 15:8 ADD[15:8] 23:16 ADD[23:16] 0x02 ADDR 0x03 31:24 ADD[31:24] 0x04 7:0 BYTE_COUNT[7:0] 0x05 0x06 PCKSIZE 0x07 15:8 31:24 0x08 Reserved 7:0 0x09 Reserved 15:8 0x0A STATUS_BK 7:0 0x0B Reserved 7:0 0x0C Reserved 7:0 0x0D Reserved 7:0 0x0E Reserved 7:0 0x0F Reserved 7:0 38.7.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus ...........continued Offset Name 0x1A Reserved 0x1B Reserved 0x1C 0x1D INTFLAG 0x1E Reserved 0x1F Reserved 0x20 0x21 0x22 PINTSMRY Bit Pos. 7:0 RAMACER UPRSM DNRSM WAKEUP RST HSOF 15:8 DDISC 7:0 PINT[7:0] 15:8 PINT[15:8] DCONN Reserved 0x23 Table 38-6. Host Pipe Register n Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus ...........continued Offset 0x Name Bit Pos. n0 + index 0x0E 0x0F STATUS_PIPE 7:0 ERCNT[2:0] CRC16ER TOUTER PIDER DAPIDER DTGLER 15:8 Table 38-8. Host Pipe n Descriptor Bank 1 Offset 0x Name Bit Pos.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.1.1 Control A Name: Offset: Reset: Property: Bit Access Reset 7 CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronised 2 1 0 MODE 6 5 4 3 RUNSTDBY ENABLE SWRST R/W R/W R/W R/W 0 0 0 0 Bit 7 – MODE Operating Mode This bit defines the operating mode of the USB. Value Description 0 USB Device mode 1 USB Host mode Bit 2 – RUNSTDBY Run in Standby Mode This bit is Enable-Protected.
PAGE 1138
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.1.2 Synchronization Busy Name: Offset: Reset: Property: Bit 7 SYNCBUSY 0x02 0x00 - 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Synchronization Enable status bit This bit is cleared when the synchronization of ENABLE register between the clock domains is complete. This bit is set when the synchronization of ENABLE register between clock domains is started.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.1.3 QOS Control Name: Offset: Reset: Property: Bit 7 QOSCTRL 0x03 0x0F PAC Write-Protection 6 5 4 3 2 1 DQOS[1:0] Access Reset 0 CQOS[1:0] R/W R/W R/W R/W 1 1 1 1 Bits 3:2 – DQOS[1:0] Data Quality of Service These bits define the memory priority access during the endpoint or pipe read/write data operation. Refer to SRAM Quality of Service.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.1.4 Finite State Machine Status Name: Offset: Reset: Property: Bit 7 FSMSTATUS 0x0D 0xXXXX Read only 6 5 4 3 2 1 0 FSMSTATE[6:0] Access R R R R R R R Reset 0 0 0 0 0 0 1 Bits 6:0 – FSMSTATE[6:0] Fine State Machine Status These bits indicate the state of the finite state machine of the USB controller. Value Name Description 0x01 OFF (L3) Corresponds to the powered-off, disconnected, and disabled state.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.1.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.1.6 Pad Calibration Name: Offset: Reset: Property: PADCAL 0x28 0x0000 PAC Write-Protection The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration register by software, before enabling the USB, to achieve the specified accuracy. Refer to NVM Software Calibration Area Mapping for further details. Refer to for further details.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.1 Control B Name: Offset: Reset: Property: Bit 15 CTRLB 0x08 0x0000 PAC Write-Protection 14 13 12 11 10 LPMHDSK[1:0] Access Reset Bit 7 6 5 4 NREPLY 9 8 GNAK R/W R/W R/W 0 0 0 3 2 1 0 UPRSM DETACH Access R R/W SPDCONF[1:0] R/W R/W R/W Reset 0 0 0 0 0 Bits 11:10 – LPMHDSK[1:0] Link Power Management Handshake These bits select the Link Power Management Handshake configuration.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 0x3 Description Reserved Bit 1 – UPRSM Upstream Resume This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent. Value Description 0 Writing a zero to this bit has no effect. 1 Writing a one to this bit will generate an upstream resume to the host for a remote wakeup. Bit 0 – DETACH Detach Value Description 0 The device is attached to the USB bus so that communications may occur.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.2 Device Address Name: Offset: Reset: Property: Bit 7 DADD 0x0A 0x00 PAC Write-Protection 6 5 4 ADDEN Access Reset 3 2 1 0 DADD[6:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – ADDEN Device Address Enable This bit is cleared when a USB reset is received. Value Description 0 Writing a zero will deactivate the DADD field (USB device address) and return the device to default address 0.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.3 Status Name: Offset: Reset: Property: Bit STATUS 0x0C 0x40 - 7 6 5 4 3 LINESTATE[1:0] 2 1 0 SPEED[1:0] Access R R R/W R/W Reset 0 1 0 1 Bits 7:6 – LINESTATE[1:0] USB Line State Status These bits define the current line state DP/DM. LINESTATE[1:0] USB Line Status 0x0 SE0/RESET 0x1 FS-J or LS-K State 0x2 FS-K or LS-J State Bits 3:2 – SPEED[1:0] Speed Status These bits define the current speed used of the device .
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.4 Device Frame Number Name: Offset: Reset: Property: Bit 15 FNUM 0x10 0x0000 Read only 14 13 12 11 FNCERR Access 10 9 8 FNUM[10:5] R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 FNUM[4:0] Access Reset MFNUM[2:0] Bit 15 – FNCERR Frame Number CRC Error This bit is cleared upon receiving a USB reset.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.5 Device Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x0000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request. Value Description 0 The Upstream Resume interrupt is disabled. 1 The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set. Bit 5 – EORSM End Of Resume Interrupt Enable Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 1 Description The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is set. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.6 Device Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x18 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 1 Description The Upstream Resume interrupt is enabled. Bit 5 – EORSM End Of Resume Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt request. Value Description 0 The End Of Resume interrupt is disabled. 1 The End Of Resume interrupt is enabled.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.7 Device Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 15 INTFLAG 0x01C 0x0000 - 14 13 12 11 10 Access Reset Bit Access Reset 9 8 LPMSUSP LPMNYET R/W R/W 0 0 1 0 7 6 5 4 3 2 RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Flag This flag is cleared by writing a one to the flag.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Bit 4 – WAKEUP Wake Up Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB is reactivated by a filtered non-idle signal from the lines and will generate an interrupt if INTENCLR/SET.WAKEUP is one. Writing a zero to this bit has no effect. Bit 3 – EORST End of Reset Interrupt Flag This flag is cleared by writing a one to the flag.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.2.8 Endpoint Interrupt Summary Name: Offset: Reset: Property: Bit 15 EPINTSMRY 0x20 0x0000 - 14 13 12 11 10 9 8 EPINT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 EPINT[7:0] Bits 15:0 – EPINT[15:0] EndPoint Interrupt The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. See 38.8.3.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.3.1 Device Endpoint Configuration register n Name: Offset: Reset: Property: Bit 7 EPCFGn 0x100 + (n x 0x20) 0x00 PAC Write-Protection 6 5 4 3 2 EPTYPE1[2:0] Access Reset 1 0 EPTYPE0[2:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 6:4 – EPTYPE1[2:0] Endpoint Type for IN direction These bits contains the endpoint type for IN direction. Upon receiving a USB reset EPCFGn.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.3.2 EndPoint Status Clear n Name: Offset: Reset: Property: Bit EPSTATUSCLRn 0x104 + (n * 0x20) 0x00 PAC Write-Protection 7 6 5 4 2 1 0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 3 CURBK DTGLIN DTGLOUT Access W W W W W W W Reset 0 0 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.3.3 EndPoint Status Set n Name: Offset: Reset: Property: Bit EPSTATUSSETn 0x105 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 2 1 0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 3 CURBK DTGLIN DTGLOUT Access W W W W W W W Reset 0 0 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Set Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.BK1RDY bit.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.3.4 EndPoint Status n Name: Offset: Reset: Property: Bit EPSTATUSn 0x106 + (n x 0x20) 0x00 PAC Write-Protection 7 6 2 1 0 BK1RDY BK0RDY 5 STALLRQ 4 3 CURBK DTGLIN DTGLOUT Access R R R R R R Reset 0 0 2 0 0 0 Bit 7 – BK1RDY Bank 1 is ready For Control/OUT direction Endpoints, the bank is empty. Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit. Writing a one to the bit EPSTATUSSET.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 0 1 Description The PID of the next expected IN transaction will be zero: data 0. The PID of the next expected IN transaction will be one: data 1. Bit 0 – DTGLOUT Data Toggle OUT Sequence Writing a zero to the bit EPSTATUSCLR.DTGLOUTCLR will clear this bit. Writing a one to the bit EPSTATUSSET.DTGLOUTSET will set this bit. Value Description 0 The PID of the next expected OUT transaction will be zero: data 0.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.3.5 Device EndPoint Interrupt Flag n Name: Offset: Reset: Property: Bit 7 EPINTFLAGn 0x107 + (n x 0x20) 0x00 - 6 Access Reset 5 4 STALL RXSTP 3 TRFAIL 2 1 TRCPT 0 R/W R/W R/W R/W 0 0 0 0 Bit 5 – STALL Transmit Stall x Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is one. EPINTFLAG.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.3.6 Device EndPoint Interrupt Enable n Name: Offset: Reset: Property: EPINTENCLRn 0x108 + (n x 0x20) 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 1 Description The Transfer Complete bank x interrupt is enabled and an interrupt request will be generated when the Transfer Complete x Interrupt Flag is set. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.3.7 Device Interrupt EndPoint Set n Name: Offset: Reset: Property: EPINTENSETn 0x109 + (n x 0x20) 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This register is cleared by USB reset or when EPEN[n] is zero.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.4 Device Registers - Endpoint RAM 38.8.4.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.4.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.4.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus ...........continued Value Description 0x6 512 Byte(1) 0x7 1023 Byte(1) (1) for Isochronous endpoints only. Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multiple Packet Size These bits define the 14-bit value that is used for multi-packet transfers. For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written to zero when setting up a new transfer.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.4.
PAGE 1170
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.4.5 Device Status Bank Name: Offset: Reset: Property: Bit 7 STATUS_BK 0x0A & 0x1A 0xxxxxxxx NA 6 5 4 3 Access Reset 2 1 0 ERRORFLOW CRCERR R/W R/W x x Bit 1 – ERRORFLOW Error Flow Status This bit defines the Error Flow Status. This bit is set when a Error Flow has been detected during transfer from/towards this bank. For OUT transfer, a NAK handshake has been sent.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.1 Control B Name: Offset: Reset: Property: Bit 15 CTRLB 0x08 0x0000 PAC Write-Protection 14 13 12 Access Reset Bit 7 6 5 4 11 10 9 8 L1RESUME VBUSOK BUSRESET SOFE R/W R/W R/W R/W 0 0 0 0 3 2 1 0 SPDCONF[1:0] Access Reset RESUME R/W R/W R/W 0 0 0 Bit 11 – L1RESUME Send USB L1 Resume Writing 0 to this bit has no effect. 1: Generates a USB L1 Resume on the USB bus.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 0x0 0x1 0x2 0x3 Description Low and Full Speed capable Reserved Reserved Reserved Bit 1 – RESUME Send USB Resume Writing 0 to this bit has no effect. 1: Generates a USB Resume on the USB bus. This bit is cleared when the USB Resume has been sent or when a USB reset is requested. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.2 Host Start-of-Frame Control Name: Offset: Reset: Property: HSOFC 0x0A 0x00 PAC Write-Protection During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after writing, it is recommended to check the register value, and write this register again if necessary. This register is cleared upon a USB reset.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.3 Status Name: Offset: Reset: Property: Bit STATUS 0x0C 0x00 Read only 7 6 5 4 3 LINESTATE[1:0] 2 1 0 SPEED[1:0] Access R R R/W R/W Reset 0 0 0 0 Bits 7:6 – LINESTATE[1:0] USB Line State Status These bits define the current line state DP/DM.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.4 Host Frame Number Name: Offset: Reset: Property: Bit 15 FNUM 0x10 0x0000 PAC Write-Protection 14 13 12 11 10 9 8 FNUM[10:5] Access Reset Bit R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5 4 3 2 1 0 7 6 R/W R/W R/W R/W R/W 0 0 0 0 0 FNUM[4:0] Access Reset Bits 13:3 – FNUM[10:0] Frame Number These bits contains the current SOF number.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.5 Host Frame Length Name: Offset: Reset: Property: Bit 7 FLENHIGH 0x12 0x00 Read-Only 6 5 4 3 2 1 0 FLENHIGH[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – FLENHIGH[7:0] Frame Length These bits contains the 8 high-order bits of the internal frame counter. Table 38-9. Counter Description vs. Speed Host Register Description STATUS.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.6 Host Interrupt Enable Register Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x0000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request. Value Description 0 The Upstream Resume interrupt is disabled. 1 The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set. Bit 5 – DNRSM Down Resume Interrupt Disable Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.7 Host Interrupt Enable Register Set Name: Offset: Reset: Property: INTENSET 0x18 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 1180
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt. Value Description 0 The Down Resume interrupt is disabled. 1 The Down Resume interrupt is enabled. Bit 4 – WAKEUP Wake Up Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt request. Value Description 0 The WakeUp interrupt is disabled.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.8 Host Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 15 INTFLAG 0x1C 0x0000 - 14 13 12 11 10 Access Reset Bit Access Reset 7 6 5 4 3 2 RAMACER UPRSM DNRSM WAKEUP RST HSOF R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 9 8 DDISC DCONN R/W R/W 0 0 1 0 Bit 9 – DDISC Device Disconnection Interrupt Flag This flag is cleared by writing a one to the flag.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Bit 4 – WAKEUP Wake Up Interrupt Flag This flag is cleared by writing a one. This flag is set when: l The host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is detected. l The host controller is in suspend mode (SOFE is zero) and an device disconnection is detected. l The host controller is in operational state (VBUSOK is one) and an device connection is detected.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.5.9 Pipe Interrupt Summary Name: Offset: Reset: Property: Bit 15 PINTSMRY 0x20 0x0000 Read-only 14 13 12 11 10 9 8 PINT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 PINT[7:0] Bits 15:0 – PINT[15:0] The flag PINT[n] is set when an interrupt is triggered by the pipe n. See 38.8.6.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.1 Host Pipe n Configuration Name: Offset: Reset: Property: Bit PCFGn 0x100 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 PTYPE[2:0] Access Reset 1 BK 0 PTOKEN[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:3 – PTYPE[2:0] Type of the Pipe These bits contains the pipe type.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus PTOKEN[1:0](1) Description 0x0 SETUP(2) 0x1 IN 0x2 OUT 0x3 Reserved 1. 2. PTOKEN field is ignored when PTYPE is configured as EXTENDED. Available only when PTYPE is configured as CONTROL Theses bits are cleared upon sending a USB reset. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.2 Interval for the Bulk-Out/Ping Transaction Name: Offset: Reset: Property: Bit BINTERVAL 0x103 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 BINTERVAL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – BINTERVAL[7:0] BINTERVAL These bits contains the Ping/Bulk-out period. These bits are cleared when a USB reset is sent or when PEN[n] is zero.
PAGE 1187
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.3 Pipe Status Clear n Name: Offset: Reset: Property: Bit PSTATUSCLR 0x104 + (n x 0x20) 0x00 PAC Write-Protection 7 6 BK1RDY BK0RDY 5 PFREEZE 4 3 CURBK 2 1 DTGL 0 Access W W W W W Reset 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear PSTATUS.BK1RDY bit. Bit 6 – BK0RDY Bank 0 Ready Clear Writing a zero to this bit has no effect.
PAGE 1188
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.4 Pipe Status Set Register n Name: Offset: Reset: Property: Bit PSTATUSSET 0x105 + (n x 0x20) 0x00 PAC Write-Protection 7 6 BK1RDY BK0RDY 5 PFREEZE 4 3 CURBK 2 1 DTGL 0 Access W W W W W Reset 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Set Writing a zero to this bit has no effect. Writing a one to this bit will set the bit PSTATUS.BK1RDY. Bit 6 – BK0RDY Bank 0 Ready Set Writing a zero to this bit has no effect.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.5 Pipe Status Register n Name: Offset: Reset: Property: Bit PSTATUS 0x106 + (n x 0x20) 0x00 PAC Write-Protection 7 6 BK1RDY BK0RDY 5 PFREEZE 4 3 CURBK 2 1 DTGL 0 Access R R R R R Reset 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 is ready Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit. Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit. This bank is not used for Control pipe.
PAGE 1190
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Bit 2 – CURBK Current Bank Value Description 0 The bank0 is the bank that will be used in the next single/multi USB packet. 1 The bank1 is the bank that will be used in the next single/multi USB packet. Bit 0 – DTGL Data Toggle Sequence Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit. Writing a one to the bit EPSTATUSSET.DTGL will set this bit. This bit is toggled automatically by hardware after a data transaction.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.6 Host Pipe Interrupt Flag Register Name: Offset: Reset: Property: Bit 7 PINTFLAG 0x107 + (n x 0x20) 0x00 - 6 Access Reset 5 4 3 2 STALL TXSTP PERR TRFAIL 1 TRCPT 0 R/W R/W R/W R/W R/W 0 0 0 0 2 Bit 5 – STALL STALL Received Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one.
PAGE 1192
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.7 Host Pipe Interrupt Clear Register Name: Offset: Reset: Property: PINTENCLR 0x108 + (n x 0x20) 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register. This register is cleared by USB reset or when PEN[n] is zero.
PAGE 1193
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 1 Description The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail interrupt Flag is set. Bit 0 – TRCPT Transfer Complete Bank x interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Complete interrupt Enable bit x and disable the corresponding interrupt request. Value Description 0 The Transfer Complete Bank x interrupt is disabled.
PAGE 1194
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.6.8 Host Interrupt Pipe Set Register Name: Offset: Reset: Property: PINTENSET 0x109 + (n x 0x20) 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register. This register is cleared by USB reset or when PEN[n] is zero.
PAGE 1195
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Value 0 1 38.8.7 Description The Transfer Complete x interrupt is disabled. The Transfer Complete x interrupt is enabled. Host Registers - Pipe RAM 38.8.7.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.7.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.7.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus ...........continued SIZE[2:0] Description 0x6 512 Byte(1) 0x7 1024 Byte in HS mode(1) 1023 Byte in FS mode(1) 1. For Isochronous pipe only. Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multi Packet IN or OUT size These bits define the 14-bit value that is used for multi-packet transfers. For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written to zero when setting up a new transfer.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.7.
PAGE 1200
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.7.5 Host Status Bank Name: Offset: Reset: Property: Bit 7 STATUS_BK 0x0A & 0x1A 0xxxxxxxx NA 6 5 4 3 Access Reset 2 1 0 ERRORFLOW CRCERR R/W R/W x x Bit 1 – ERRORFLOW Error Flow Status This bit defines the Error Flow Status. This bit is set when a Error Flow has been detected during transfer from/towards this bank. For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.7.
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SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus 38.8.7.
PAGE 1203
SAM D5x/E5x Family Data Sheet USB – Universal Serial Bus Bit 0 – DTGLER Data Toggle Error This bit defines the Data Toggle Error Status. This bit is set when a Data Toggle Error has been detected. Value Description 0 No Data Toggle Error. 1 Data Toggle Error detected. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39. 39.1 CAN - Control Area Network Overview The Control Area Network (CAN) performs communication according to ISO 11898-1:2015 (Bosch CAN specification 2.0 part A,B, ISO CAN FD). The message storage is intended to be a single- or dual-ported Message RAM outside of the module. 39.2 Features • Conform with CAN protocol version 2.0 part A, B and ISO 11898-1:2015 • Up to two Controller Area Network CAN – Supporting CAN2.
PAGE 1205
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.3 Block Diagram Figure 39-1. CAN Block Diagram SRAM CAN High-Speed Bus AHB USER INTF CAN_TX CAN CORE CAN_RX NVIC GCLK 39.4 CAN interrupts GCLK_CAN Signal Description Table 39-1. Signal Description Signal Description Type CAN_TX CAN transmit Digital output CAN_RX CAN receive Digital input Refer to for details on the pin mapping for this peripheral. One signal can be mapped to one of several pins. 39.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.6.9 Sleep Mode Operation 39.5.3 Clocks An AHB clock (CLK_CAN_AHB) is required to clock the CAN. This clock can be configured in the Main Clock peripheral (MCLK) before using the CAN, and the default state of CLK_CAN_AHB can be found in the MCLK.AHBMASK register. A generic clock (GCLK_CAN) is required to clock the CAN. This clock must be configured and enabled in the generic clock controller before using the CAN.
PAGE 1207
SAM D5x/E5x Family Data Sheet CAN - Control Area Network the CAN Core to the Message RAM as well as providing receive message status information. The Tx Handler is responsible for the transfer of transmit messages from the Message RAM to the CAN Core as well as providing transmit status information. Acceptance filtering is implemented by a combination of up to 128 filter elements where each one can be configured as a range, as a bit mask, or as a dedicated ID filter. 39.6.2 Operating Modes 39.6.2.
PAGE 1208
SAM D5x/E5x Family Data Sheet CAN - Control Area Network After passing the acceptance filtering, received messages including Message ID and DLC are stored into a dedicated Rx Buffer or into Rx FIFO0 or Rx FIFO1. For messages to be transmitted dedicated Tx Buffers and/or a Tx FIFO or a Tx Queue can be initialized or updated. Automated transmission on reception of remote frames is not implemented. 39.6.2.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Table 39-2. Coding of DLC in CAN FD DLC 9 10 11 12 13 14 15 Number of Data Bytes 12 16 20 24 32 48 64 In CAN FD frames, the bit timing will be switched inside the frame, after the BRS (Bit Rate Switch) bit, if this bit is recessive. Before the BRS bit, in the CAN FD arbitration phase, the nominal CAN bit timing is used as defined by the Nominal Bit Timing & Prescaler Register NBTP.
PAGE 1210
SAM D5x/E5x Family Data Sheet CAN - Control Area Network • The sum of the measured delay from CAN_TX to CAN_RX and the configured transceiver delay compensation offset FBTP.TDCO has to be less than 6 bit times in the data phase. • The sum of the measured delay from CAN_TX to CAN_RX and the configured transceiver delay compensation offset FBTP.TDCO has to be less or equal to 127 mtq. In case this sum exceeds 127 mtq, the maximum value of 127 mtq is used for transceiver delay compensation.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.6.2.6 Bus Monitoring Mode The CAN is set in Bus Monitoring Mode by programming CCCR.MON to ‘1’. In Bus Monitoring Mode (see ISO 11898-1, 10.12 Bus monitoring), the CAN is able to receive valid data frames and valid remote frames, but cannot start a transmission. In this mode, it sends only recessive bits on the CAN bus.
PAGE 1212
SAM D5x/E5x Family Data Sheet CAN - Control Area Network In case of a successful frame transmission, and if storage of Tx events is enabled, a Tx Event FIFO element is written with Event Type ET = “10” (transmission in spite of cancellation). 39.6.2.8 Test Modes To enable write access to register TEST, bit CCCR.TEST has to be set to ‘1’. This allows the configuration of the test modes and test functions. Four output functions are available for the CAN transmit pin CAN_TX by programming TEST.TX.
PAGE 1213
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Figure 39-4. Pin Control in Loop Back Modes CAN_TX CAN_RX CAN_TX CAN_RX =1 TX HANDLER TX HANDLER RX HANDLER CAN CAN External Loop Back Mode 39.6.3 RX HANDLER Internal Loop Back Mode Timestamp Generation For timestamp generation the CAN supplies a 16-bit wrap-around counter. A prescaler TSCC.TCP can be configured to clock the counter in multiples of CAN bit times (1…16). The counter is readable via TSCV.TSC.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.6.5.1 Acceptance Filtering The CAN offers the possibility to configure two sets of acceptance filters, one for standard identifiers and one for extended identifiers. These filters can be assigned to an Rx Buffer or to Rx FIFO 0,1. For acceptance filtering each list of filters is executed from element #0 until the first matching element. Acceptance filtering stops at the first matching element.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Range Filter The filter matches for all received frames with Message IDs in the range defined by SF1ID/SF2ID for standard frames or EF1ID/EF2ID for extended frames.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Figure 39-5. Standard Message ID Filtering valid frame received 11-bit 29-bit 11 / 29 bit identifier yes remote frame reject remote frames SIDFC.LSS[7:0] = 0 no GFC.RRFS = '1' GFC.RRFS = '0' receive filter list enabled SIDFC.LSS[7:0] > 0 yes match filter element #0 match filter element #SIDFC.LSS no accept non-matching frames yes acceptance / rejection reject accept GFC.ANFS[1] = '1' discard frame GFC.
PAGE 1217
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Figure 39-6. Extended Message ID Filtering valid frame received 11-bit GFC.RRFE = '1' 11 / 29 bit identifier 29-bit yes reject remote frames remote frame no GFC.RRFE = '0' XIDFC.LSE[6:0] > 0 yes match filter element #0 reject acceptance / rejection yes accept GFC.ANFE[1] = '1' discard frame XIDFC.LSE[6:0] = 0 receive filter list enabled match filter element #XIDFC.LSE no accept non-matching frames GFC.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Figure 39-7. Rx FIFO Status Get Index RXFnS.FnGI 7 Put Index RXFnS.FnPI 0 6 1 5 2 4 3 Fill Level RXFnS.FnFI When reading from an Rx FIFO, Rx FIFO Get Index RXFnS.FnGI • FIFO Element Size has to be added to the corresponding Rx FIFO start address RXFnC.FnSA. Table 39-3. Rx Buffer / FIFO Element Size RXESC.RBDS[2:0] RXESC.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network When an Rx FIFO full condition (RXFnS.FnPI = RXFnS.FnGI) is signaled by RXFnS.FnF = ‘1’, the next message accepted for the FIFO will overwrite the oldest FIFO message. Put and get index are both incremented by one. When an Rx FIFO is operated in overwrite mode and an Rx FIFO full condition is signaled, reading of the Rx FIFO elements should start at least at get index + 1.
PAGE 1220
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Table 39-4. Example Filter Configuration for Rx Buffers Filter Element SFID1[10:0] / EFID1[28:0] SFID2[10:9] / EFID2[10:9] SFID2[5:0] / EFID2[5:0] 0 ID message 1 00 00 0000 1 ID message 2 00 00 0001 2 ID message 3 00 00 0010 After the last word of a matching received message has been written to the Message RAM, the respective New Data flag in register NDAT1, NDAT2 is set.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network When a debug message is stored, neither the respective New Data flag nor IR.DRX are set. The reception of debug messages can be monitored via RXF1S.DMS. Table 39-5.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Table 39-6.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network A Dedicated Tx Buffer allocates Element Size 32-bit words in the Message RAM (refer to table below). Therefore the start address of a dedicated Tx Buffer in the Message RAM is calculated by adding transmit buffer index (0…31) • Element Size to the Tx Buffer Start Address TXBC.TBSA. Table 39-7. Tx Buffer / FIFO / Queue Element Size TXESC.
PAGE 1224
SAM D5x/E5x Family Data Sheet CAN - Control Area Network multiple Queue Buffers are configured with the same Message ID, the Queue Buffer with the lowest buffer number is transmitted first. New messages have to be written to the Tx Buffer referenced by the Put Index TXFQS.TFQPI. An Add Request cyclically increments the Put Index to the next free Tx Buffer. In case that the Tx Queue is full (TXFQS.
PAGE 1225
SAM D5x/E5x Family Data Sheet CAN - Control Area Network • Tx Buffer with lowest Message ID gets highest priority and is transmitted next 39.6.6.7 Transmit Cancellation The CAN supports transmit cancellation. This feature is especially intended for gateway applications and AUTOSAR based applications. To cancel a requested transmission from a dedicated Tx Buffer or a Tx Queue Buffer the CPU has to write a ‘1’ to the corresponding bit position (=number of Tx Buffer) of register TXBCR.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network reading a High Priority Message from one of the two Rx FIFOs. In this case the FIFO’s Acknowledge Index should not be written because this would set the Get Index to a wrong position and also alters the FIFO’s Fill Level. In this case some of the older FIFO elements would be lost. Note: The application has to ensure that a valid value is written to the FIFO Acknowledge Index. The CAN does not check for erroneous values. 39.6.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network register (CCCR.CSR = 1). Once all pending transactions are completed and the idle bus state is detected, the CAN will automatically set the Clock Stop Acknowledge bit (CCCR.CSA = 1). The CAN then reverts back to its initial state (CCCR.INIT = 1), blocking further transfers, and it is now safe for CLK_CANx_APB and GCLK_CANx to be switched off and the system may go to standby.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.7 Offset Register Summary Name Bit Pos.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network ...........continued Offset Name Bit Pos. 7:0 0x28 0x2C TOCC TOCV TOS[1:0] ETOC 15:8 23:16 TOP[7:0] 31:24 TOP[15:8] 7:0 TOC[7:0] 15:8 TOC[15:8] 23:16 31:24 0x30 ... Reserved 0x3F 7:0 0x40 ECR 15:8 TEC[7:0] RP REC[6:0] 23:16 CEL[7:0] 31:24 7:0 0x44 PSR BO 15:8 EW EP PXE RFDF ACT[1:0] RBRS 23:16 LEC[2:0] RESI DLEC[2:0] TDCV[6:0] 31:24 0x48 TDCR 7:0 TDCF[6:0] 15:8 TDCO[6:0] 23:16 31:24 0x4C ...
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network ...........continued Offset Name Bit Pos. 7:0 0x80 GFC ANFS[1:0] ANFE[1:0] RRFS RRFE RF0L F0F 15:8 23:16 31:24 0x84 SIDFC 7:0 FLSSA[7:0] 15:8 FLSSA[15:8] 23:16 LSS[7:0] 31:24 0x88 XIDFC 7:0 FLESA[7:0] 15:8 FLESA[15:8] 23:16 LSE[6:0] 31:24 0x8C ...
PAGE 1231
SAM D5x/E5x Family Data Sheet CAN - Control Area Network ...........continued Offset 0xAC Name RXBC Bit Pos.
PAGE 1232
SAM D5x/E5x Family Data Sheet CAN - Control Area Network ...........continued Offset 0xD8 0xDC 0xE0 0xE4 Name TXBTO TXBCF TXBTIE TXBCIE Bit Pos. 7:0 TOn[7:0] 15:8 TOn[15:8] 23:16 TOn[23:16] 31:24 TOn[31:24] 7:0 CFn[7:0] 15:8 CFn[15:8] 23:16 CFn[23:16] 31:24 CFn[31:24] 7:0 TIEn[7:0] 15:8 TIEn[15:8] 23:16 TIEn[23:16] 31:24 TIEn[31:24] 7:0 CFIEn[7:0] 15:8 CFIEn[15:8] 23:16 CFIEn[23:16] 31:24 CFIEn[31:24] 0xE8 ...
PAGE 1233
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.1 Core Release Name: Offset: Reset: Property: CREL 0x00 0x32100000 Read-only Bit 31 30 29 28 27 26 Access R Reset Bit 25 24 R R R R R 0 0 1 1 R R 0 0 1 0 23 22 21 20 19 18 17 16 REL[3:0] STEP[3:0] SUBSTEP[3:0] Access R R R R Reset 0 0 0 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bits 31:28 – REL[3:0] Core Release One digit, BCD-coded.
PAGE 1234
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
PAGE 1235
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.3 Message RAM Configuration Name: Offset: Reset: Property: Bit MRCFG 0x08 0x00000002 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 DQOS[1:0] Access Reset R/W R/W 1 0 Bits 1:0 – DQOS[1:0] Data Quality of Service This field defines the memory priority access during the Message RAM read/write data operation.
PAGE 1236
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.4 Data Bit Timing and Prescaler Name: Offset: Reset: Property: DBTP 0x0C 0x00000A33 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1. The CAN bit time may be programmed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 GCLK_CAN periods. tq = (DBRP + 1) mtq.
PAGE 1237
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bits 12:8 – DTSEG1[4:0] Fast time segment before sample point Value Description 0x00 - Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that 0x1F one more than the programmed value is used. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. Bits 7:4 – DTSEG2[3:0] Data time segment after sample point Value Description 0x0 Valid values are 0 to 15.
PAGE 1238
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.5 Test Name: Offset: Reset: Property: Bit TEST 0x10 0x00000000 Read-only, Write-restricted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit RX 5 TX[1:0] LBCK Access R R/W R/W R/W Reset 0 0 0 0 Bit 7 – RX Receive Pin Monitors the actual value of pin CAN_RX Value Description 0 The CAN bus is dominant (CAN_RX = 0).
PAGE 1239
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.6 RAM Watchdog Name: Offset: Reset: Property: RWD 0x14 0x00000000 Read-only, Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the CAN’s AHB Master Interface starts the Message RAM Watchdog Counter with the value configured by RWD.WDC. The counter is reloaded with RWD.
PAGE 1240
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
PAGE 1241
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Value 0 1 Description Bit rate switching for transmissions disabled. Bit rate switching for transmissions enabled. Bit 8 – FDOE FD Operation Enable Value Description 0 FD operation disabled. 1 FD operation enabled. Bit 7 – TEST Test Mode Enable This bit field is write-restricted. Writing a 0 to this field is always allowed. Writing a 1 to this field is only allowed if bit fields CCE = 1 and INIT = 1. Value Description 0 Normal operation.
PAGE 1242
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 1 – CCE Configuration Change Enable This bit field is write-restricted and only writable if bit field INIT = 1. Value Description 0 The CPU has no write access to the protected configuration registers. 1 The CPU has write access to the protected configuration registers (while CCCR.INIT = 1).
PAGE 1243
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.8 Nominal Bit Timing and Prescaler Name: Offset: Reset: Property: NBTP 0x1C 0x00000A33 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1. The CAN bit time may be programmed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 GCLK_CAN periods. tq = (NBRP + 1) mtq.
PAGE 1244
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Value 0x00 0x7F Description Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. NTSEG1 is the sum of Prop_Seg and Phase_Seg1. Bits 6:0 – NTSEG2[6:0] Time segment after sample point Value Description 0x00 - Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that 0x7F one more than the programmed value is used.
PAGE 1245
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.9 Timestamp Counter Configuration Name: Offset: Reset: Property: TSCC 0x20 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
PAGE 1246
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.10 Timestamp Counter Value Name: Offset: Reset: Property: TSCV 0x24 0x00000000 Read-only Note: 1. A write access to TSCV while in internal mode clears the Timestamp Counter value. A write access to TSCV while in external mode has no impact. 2. A “wrap around” is a change of the Timestamp Counter value from non-zero to zero not caused by the write access to TSCV.
PAGE 1247
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.11 Timeout Counter Configuration Name: Offset: Reset: Property: TOCC 0x28 0xFFFF0000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
PAGE 1248
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.12 Timeout Counter Value Name: Offset: Reset: Property: TOCV 0x2C 0x0000FFFF Read-only Note: A write access to TOCV reloads the Timeout Counter with the value of TOCV.TOP.
PAGE 1249
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.13 Error Counter Name: Offset: Reset: Property: ECR 0x40 0x00000000 Read-only Note: When CCCR.ASM is set, the CAN protocol controller does not increment TECand REC when a CAN protocol error is detected, but CEL is still incremented.
PAGE 1250
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.14 Protocol Status Name: Offset: Reset: Property: PSR 0x44 0x00000707 Read-only Note: 1. When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in FLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. 2. The Bus_Off recovery sequence (see CAN Specification Rev. 2.
PAGE 1251
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 14 – PXE Protocol Exception Event This field is cleared on read access. Value Description 0 No protocol exception event occurred since last read access. 1 Protocol exception event occurred. Bit 13 – RFDF Received a CAN FD Message This field is cleared on read access. Value Description 0 Since this bit was reset by the CPU, no CAN FD message has been received. 1 Message in CAN FD format with FDF flag set has been received.
PAGE 1252
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Value 0x0 0x1 0x2 0x3 Name SYNC IDLE RX TX Description Node is synchronizing on CAN communication. Node is neither receiver nor transmitter. Node is operating as receiver. Node is operating as transmitter. Bits 2:0 – LEC[2:0] Last Error Code The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error.
PAGE 1253
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.15 Transmitter Delay Compensation Name: Offset: Reset: Property: TDCR 0x48 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
PAGE 1254
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.16 Interrupt Name: Offset: Reset: Property: IR 0x50 0x00000000 - The flags are set when one of the listed conditions is detected (edge-sensitive). A flag is cleared by writing a 1 to the corresponding bit field. Writing a 0 has no effect. A hard reset will clear the register.
PAGE 1255
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 25 – BO Bus_Off Status Value Description 0 Bus_Off status unchanged. 1 Bus_Off status changed. Bit 24 – EW Error Warning Status Value Description 0 Error_Warning status unchanged. 1 Error_Warning status changed. Bit 23 – EP Error Passive Value Description 0 Error_Passive status unchanged. 1 Error_Passive status changed. Bit 22 – ELO Error Logging Overflow Value Description 0 CAN Error Logging Counter did not overflow.
PAGE 1256
SAM D5x/E5x Family Data Sheet CAN - Control Area Network • has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. • was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp.
PAGE 1257
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 9 – TC Value 0 1 Timestamp Completed Description No transmission completed. Transmission completed. Bit 8 – HPM High Priority Message Value Description 0 No high priority message received. 1 High priority message received. Bit 7 – RF1L Rx FIFO 1 Message Lost Value Description 0 No Rx FIFO 1 message lost. 1 Rx FIFO 1 message lost. also set after write attempt to Rx FIFO 1 of size zero.
PAGE 1258
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.17 Interrupt Enable Name: Offset: Reset: Property: IE 0x54 0x00000000 - The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signalled on an interrupt line.
PAGE 1259
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 25 – BOE Bus_Off Status Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 24 – EWE Error Warning Status Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 23 – EPE Error Passive Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 22 – ELOE Error Logging Overflow Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
PAGE 1260
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 15 – TEFLE Tx Event FIFO Event Lost Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 14 – TEFFE Tx Event FIFO Full Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 13 – TEFWE Tx Event FIFO Watermark Reached Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 12 – TEFNE Tx Event FIFO New Entry Interrupt Enable Value Description 0 Interrupt disabled.
PAGE 1261
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 5 – RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 4 – RF1NE Rx FIFO 1 New Message Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 3 – RF0LE Rx FIFO 0 Message Lost Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled. Bit 2 – RF0FE Rx FIFO 0 Full Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
PAGE 1262
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.18 Interrupt Line Select Name: Offset: Reset: Property: ILS 0x58 0x00000000 - The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from IR to one of the two module interrupt lines.
PAGE 1263
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 25 – BOL Bus_Off Status Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0. 1 Interrupt assigned to CAN interrupt line 1. Bit 24 – EWL Error Warning Status Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0. 1 Interrupt assigned to CAN interrupt line 1. Bit 23 – EPL Error Passive Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0.
PAGE 1264
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 15 – TEFLL Tx Event FIFO Event Lost Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0. 1 Interrupt assigned to CAN interrupt line 1. Bit 14 – TEFFL Tx Event FIFO Full Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0. 1 Interrupt assigned to CAN interrupt line 1. Bit 13 – TEFWL Tx Event FIFO Watermark Reached Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0.
PAGE 1265
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 5 – RF1WL Rx FIFO 1 Watermark Reached Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0. 1 Interrupt assigned to CAN interrupt line 1. Bit 4 – RF1NL Rx FIFO 1 New Message Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0. 1 Interrupt assigned to CAN interrupt line 1. Bit 3 – RF0LL Rx FIFO 0 Message Lost Interrupt Line Value Description 0 Interrupt assigned to CAN interrupt line 0.
PAGE 1266
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.19 Interrupt Line Enable Name: Offset: Reset: Property: Bit ILE 0x5C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 EINTn[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – EINTn[1:0] Enable Interrupt Line n [n = 1,0] Value Description 0 CAN interrupt line n disabled. 1 CAN interrupt line n enabled.
PAGE 1267
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.20 Global Filter Configuration Name: Offset: Reset: Property: GFC 0x80 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
PAGE 1268
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bit 0 – RRFE Reject Remote Frames Extended Value Description 0 Filter remote frames with 29-bit extended IDs. 1 Reject all remote frames with 29-bit extended IDS. © 2019 Microchip Technology Inc.
PAGE 1269
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.21 Standard ID Filter Configuration Name: Offset: Reset: Property: SIDFC 0x84 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
PAGE 1270
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
PAGE 1271
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.23 Extended ID AND Mask Name: Offset: Reset: Property: XIDAM 0x90 0x1FFFFFFF Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
PAGE 1272
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.24 High Priority Message Status Name: Offset: Reset: Property: HPMS 0x94 0x00000000 Read-only This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
PAGE 1273
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
PAGE 1274
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
PAGE 1275
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
PAGE 1276
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bits 15:0 – F0SA[15:0] Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM. When the CAN module addresses the Message RAM it addresses 32-bit words, not single bytes. The configurable start addresses are 32-bit word addresses, i.e. only bits 15 to 2 are evaluated, the two least significant bits are ignored. Bits 1 to 0 will always be read back as “00”. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.30 Rx Buffer Configuration Name: Offset: Reset: Property: RXBC 0xAC 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.31 Rx FIFO 1 Configuration Name: Offset: Reset: Property: RXF1C 0xB0 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bits 15:0 – F1SA[15:0] Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM. When the CAN module addresses the Message RAM it addresses 32-bit words, not single bytes. The configurable start addresses are 32-bit word addresses, i.e. only bits 15 to 2 are evaluated, the two least significant bits are ignored. Bits 1 to 0 will always be read back as “00”. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bits 21:16 – F1PI[5:0] Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63. Bits 13:8 – F1GI[5:0] Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. Bits 6:0 – F1FL[6:0] Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.34 Rx Buffer / FIFO Element Size Configuration Name: Offset: Reset: Property: RXESC 0xBC 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1. Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Name DATA8 DATA12 DATA16 DATA20 DATA24 DATA32 DATA48 DATA64 Description 8 byte data field. 12 byte data field. 16 byte data field. 20 byte data field. 24 byte data field. 32 byte data field. 48 byte data field. 64 byte data field.
PAGE 1287
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.35 Tx Buffer Configuration Name: Offset: Reset: Property: TXBC 0xC0 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1. Note: Be aware that the sum of TFQS and NDTB may not be greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
PAGE 1288
SAM D5x/E5x Family Data Sheet CAN - Control Area Network Bits 15:0 – TBSA[15:0] Tx Buffers Start Address Start address of Tx Buffers section in Message RAM. When the CAN module addresses the Message RAM it addresses 32-bit words, not single bytes. The configurable start addresses are 32-bit word addresses, i.e. only bits 15 to 2 are evaluated, the two least significant bits are ignored. Bits 1 to 0 will always be read back as “00”. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.36 Tx FIFO/Queue Status Name: Offset: Reset: Property: TXFQS 0xC4 0x00000000 Read-only Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indexes indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
PAGE 1290
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.37 Tx Buffer Element Size Configuration Name: Offset: Reset: Property: TXESC 0xC8 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes >8 bytes are intended for CAN FD operation only.
PAGE 1291
SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.38 Tx Buffer Request Pending Name: Offset: Reset: Property: TXBRP 0xCC 0x00000000 Read-only Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is canceled immediately, the corresponding TXBRP bit is reset.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. Value Description 0 No transmission request pending. 1 Transmission request pending. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.39 Tx Buffer Add Request Name: Offset: Reset: Property: TXBAR 0xD0 0x00000000 - Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit is already set), this add request is ignored.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.45 Tx Event FIFO Configuration Name: Offset: Reset: Property: TXEFC 0xF0 0x00000000 Write-restricted This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 39.8.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Figure 39-12. Message RAM Configuration Start Address SIDFC.FLSSA XIDFC.FLESA RXF0C.F0SA 11-bit Filter 0-128 elements / 0-128 words 29-bit Filter 0-64 elements / 0-128 words Rx FIFO 0 0-64 elements / 0-1152 words Rx FIFO 1 0-64 elements / 0-1152 words Rx Buffers 0-64 elements / 0-1152 words RXF1C.F1SA max 4352 words RXBC.RBSA TXEFC.EFSA TXBC.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network 0 : Transmitting node is error active. 1 : Transmitting node is error passive. • R0 Bit 30 - XTD: Extended Identifier Signals to the Host whether the received frame has a standard or extended identifier. 0 : 11-bit standard identifier. 1 : 29-bit extended identifier. • R0 Bit 29 - RTR: Remote Transmission Request Signals to the Host whether the received frame is a data frame or a remote frame. 0 : Received frame is a data frame.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network • • • • • • • • R2 Bits 31:24 - DB3[7:0]: Data Byte 3 R2 Bits 23:16 - DB2[7:0]: Data Byte 2 R2 Bits 15:8 - DB1[7:0]: Data Byte 1 R2 Bits 7:0 - DB0[7:0]: Data Byte 0 R3 Bits 31:24 - DB7[7:0]: Data Byte 7 R3 Bits 23:16 - DB6[7:0]: Data Byte 6 R3 Bits 15:8 - DB5[7:0]: Data Byte 5 R3 Bits 7:0 - DB4[7:0]: Data Byte 4 ...
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Note: The ESI bit of the transmit buffer is OR’ed with the error passive flag to decide the value of the ESI bit in the transmitted FD frame. As required by the CAN FD protocol specification, an error active node may optionally transmit the ESI bit recessive, but an error passive node will always transmit the ESI bit recessive. • T0 Bit 30 - XTD: Extended Identifier 0 : 11-bit standard identifier. 1 : 29-bit extended identifier.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network • T3 Bits 23:16 - DB6[7:0]: Data Byte 6 • T3 Bits 15:8 - DB5[7:0]: Data Byte 5 • T3 Bits 7:0 - DB4[7:0]: Data Byte 4 • • • • ... Tn Bits 31:24 - DBm[7:0]: Data Byte m Tn Bits 23:16 - DBm-1[7:0]: Data Byte m-1 Tn Bits 15:8 - DBm-2[7:0]: Data Byte m-2 Tn Bits 7:0 - DBm-3[7:0]: Data Byte m-3 Note: Depending on the configuration of TXESC, between two and sixteen 32-bit words (Tn = 3 ... 17) are used for storage of a CAN message’s data field. 39.9.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Table 39-11. Event Type Value Name Description 0x0 or 0x3 RES Reserved 0x1 TXE Tx event 0x2 TXC Transmission in spite of cancellation (always set for transmission in DAR mode) • E1 Bit 21 - FDF: FD Format 0 : Standard frame format. 1 : CAN FD frame format (new DLC-coding and CRC). • E1 Bit 20 - BRS: Bit Rate Search 0 : Frame received without bit rate switching. 1 : Frame received with bit rate switching.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network • Bits 29:27 - SFEC[2:0]: Standard Filter Element Configuration All enabled filter elements are used for acceptance filtering of standard frames. Acceptance filtering stops at the first matching enabled filter element or when the end of the filter list is reached. If SFEC = “100”, “101”, or “110” a match sets interrupt flag IR.HPM and, if enabled, an interrupt is generated. In this case register HPMS is updated with the status of the priority match.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network Table 39-15. Extended Message ID Filter Element 31 3 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 F0 F1 EFEC EFID1[28:0] [2:0] EFT EFID2[28:0] [1:0] • F0 Bits 31:29 - EFEC[2:0]: Extended Filter Element Configuration All enabled filter elements are used for acceptance filtering of extended frames.
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SAM D5x/E5x Family Data Sheet CAN - Control Area Network This bit field has a different meaning depending on the configuration of EFEC. 1) EFEC = “001” ... “110” Second ID of standard ID filter element. 2) EFEC = “111” Filter for Rx Buffers or for debug messages. EFID2[10:9] decides whether the received message is stored into an Rx Buffer or treated as message A, B, or C of the debug message sequence.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40. SD/MMC Host Controller (SDHC) 40.1 Overview The SD/MMC Host Controller (SDHC) supports the embedded MultiMedia Card (e.MMC) Specification, the SD Memory Card Specification, and the SDIO Specification. It is compliant with the SD Host Controller Standard specifications. Refer to 40.1.1 Reference Documents for details. The SDHC includes the register set defined in the “SD Host Controller Simplified Specification V3.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... • Internal 1024-byte Dual Port RAM • Support for both synchronous and asynchronous abort • Supports for SDIO Card Interrupt 40.3 Block Diagrams 40.3.1 Block Diagram SDHC SDCD SDCMD SDWP SDCK SDDAT[3:0] CLK_AHB_SDHCx GCLK_SDHCx GCLK_SDHCx_SLOW © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.3.2 Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer SD/MMC Host Controller (SDHC) MMC/e.MMC 40.4 SDCard SDIO Signal Description Signal Name Type Description SDCD Input SD Card / SDIO /e.MMC Card Detect SDCMD I/O SD Card / SDIO /e.MMC Command/Response Line SDWP Input SD Card Connector Write Protect Signal SDCK Output SD Card / SDIO /e.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... The two generic clocks are: • The core clock GCLK_SDHCx is required to clock the SDHC core. • The slow clock GCLK_SDHCx_SLOW is only required for certain functions. When this clock is required, GCLK_SDHCx must be enabled. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SDHC. The generic clocks are asynchronous to the user interface clock (CLK_SDHCx_AHB).
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.7 Offset Register Summary Name Bit Pos.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... ...........continued Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... ...........continued Offset Name Bit Pos. 0x55 ... Reserved 0x57 0x58 ASAR 7:0 ADMASA[7:0] 15:8 ADMASA[15:8] 23:16 ADMASA[23:16] 31:24 ADMASA[31:24] 7:0 SDCLKFSEL[7:0] 0x5C ...
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... ...........continued Offset Name Bit Pos. 7:0 0x0208 ACR BMAX[1:0] 15:8 23:16 31:24 7:0 0x020C CC2R FSDCLKD 15:8 23:16 31:24 0x0210 ... Reserved 0x022F 7:0 0x0230 CACR 15:8 CAPWREN KEY[7:0] 23:16 31:24 0x0234 40.8 DBGR 7:0 NIDBG 15:8 Register Description © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.1 SDMA System Address / Argument 2 Register Name: Offset: Reset: Property: SSAR 0x00 0x00000000 - This register contains the physical system memory address used for SDMA transfers or the second argument for Auto CMD23.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.2 Block Size Register Name: Offset: Reset: Property: Bit 15 BSR 0x04 0x0000 - 14 13 12 11 10 9 BOUNDARY[2:0] BLKSIZE[9:8] Access Reset Bit 7 8 0 0 0 6 5 4 R/W R/W 0 0 3 2 1 0 BLKSIZE[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 14:12 – BOUNDARY[2:0] SDMA Buffer Boundary This field specifies the size of the contiguous buffer in the system memory.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.3 Block Count Register Name: Offset: Reset: Property: Bit BCR 0x06 0x0000 - 15 14 13 12 11 R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 BLKCNT[15:8] Access BLKCNT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – BLKCNT[15:0] Block Count for Current Transfer This field is used only if TMR.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.5 Transfer Mode Register Name: Offset: Reset: Property: TMR 0x0C 0x0000 - This register is used to control data transfers. The user shall set this register before issuing a command which transfers data (refer to bit DPSEL in CR), or before issuing a Resume command. The user must save the value of this register when the data transfer is suspended (as a result of a Suspend command) and restore it before issuing a Resume command.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 2. Auto CMD23: when the ACMDEN field is set to 2, the peripheral issues a CMD23 automatically before issuing a command specified in CR. The following conditions are required to use Auto CMD23: • A memory card that supports CMD23 (SCR[33] = 1) • If DMA is used, it must be ADMA (SDMA not supported). • Only CMD18 or CMD25 is issued. Note: The peripheral does not check the command index. Auto CMD23 can be used with or without ADMA.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 1 Name ENABLED Description The Command Index Check is enabled. Bit 3 – CMDCCEN Command CRC Check Enable If this bit is set to 1, the peripheral checks the CRC field in the response. If an error is detected, it is reported as a Command CRC Error (CMDCRC) in EISTR. If this bit is set to 0, the CRC field is not checked. The position of the CRC field is determined according to the length of the response.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.7 Response Register n Name: Offset: Reset: Property: RR 0x10 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... ...........continued Type of response Meaning of response Response field Response register R6 (Published RCA response) New published RCA[31:16] and Card status bits R[39:8] © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 17 – CARDSS Card State Stable This bit is used for testing. If it is 0, the CARDDPL is not stable. If this bit is set to 1, it means that the CARDDPL is stable. No Card state can be detected if this bit is set to 1 and CARDINS is set to 0. The Software Reset For All (SWRSTALL) in SRR does not affect this bit.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 8 – WTACT Write Transfer Active This bit indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the peripheral. Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for more details on the sequence of events. This bit is set to 1 in either of the following conditions: • After the end bit of the write command.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... The peripheral stops a read operation at the start of the interrupt cycle by driving the Read Wait (DAT[2] line) or by stopping the SD Clock. If the Read Wait signal is already driven (due to the fact that the data buffer cannot receive data), the peripheral can continue to stop the read operation by driving the Read Wait signal. It is necessary to support the Read Wait in order to use the Suspend/Resume operation.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Even if the Command Inhibit (DAT) is set to 1, commands using only the CMD line can be issued if this bit is 0. A change from 1 to 0 rises the Command Complete (CMDC) status flag in NISTR if NISTER.CMDC is set to 1. An interrupt is generated if NISIER.CMDC is set to 1. If the peripheral cannot issue the command because of a command conflict error (refer to CMDCRC in EISTR) or because of a ‘Command Not Issued By Auto CMD12’ error (refer to Section 1.2.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.10 Host Control 1 Register Name: Offset: Reset: Property: Bit Access Reset HC1R 0x28 0x00 - 7 6 CARDDSEL CARDDTL R/W R/W 0 0 5 4 3 DMASEL[1:0] 0 0 2 1 0 HSEN DW LEDCTRL R/W R/W R/W 0 0 0 Bit 7 – CARDDSEL Card Detect Signal Selection Note: This register entry is specific to the SD/SDIO operation mode. This bit selects the source for the card detection. Value Description 0 The CD pin is selected.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 1 Description High Speed mode. Note: 1. This bit is effective only if MC1R.DDR is set to 0. 2. The clock divider (DIV) in CCR must be set to a value different from 0 when HSEN is 1. Bit 1 – DW Data Width This bit selects the data width of the peripheral. It must be set to match the data width of the card. Note: If the Extended Data Transfer Width is 1, this bit has no effect and the data width is 8-bit mode.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.11 Power Control Register Name: Offset: Reset: Property: Bit 7 PCR 0x29 0x0E - 6 5 4 3 2 1 SDBVSEL[2:0] Access Reset 0 SDBPWR R/W R/W R/W R/W 1 1 1 0 Bits 3:1 – SDBVSEL[2:0] SD Bus Voltage Select By setting this bit, the user selects the voltage level for the card. Before setting this register, the user must check the Voltage Support in CA0R. If an unsupported voltage is selected, the system does not supply the bus voltage.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.12 Block Gap Control Register Name: Offset: Reset: Property: Bit 7 BGCR 0x2A 0x00 - 6 Access Reset 5 4 3 2 1 0 INTBG RWCTRL CONTR STPBGR R/W R/W R/W R/W 0 0 0 0 Bit 3 – INTBG Interrupt at Block Gap Note: This register entry is specific to the SD/SDIO operation mode. This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 0 1 Description No affect Restart Bit 0 – STPBGR Stop At Block Gap Request This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. The user must leave this bit set to 1 until Transfer Complete (TRFC) in NISTR. Clearing both Stop At Block Gap Request and Continue Request does not cause the transaction to restart.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.13 Wakeup Control Register: SD/SDIO Name: Offset: Reset: Property: Bit 7 WCR 0x2B 0x00 - 6 5 4 3 Access Reset 2 1 0 WKENCREM WKENCINS WKENCINT R/W R/W R/W 0 0 0 Bit 2 – WKENCREM Wake-up Event Enable on Card Removal This bit enables a wake-up event via Card Removal (CREM) in NISTR. FN_WUS (Wake-Up Support) in the CIS (Card Information Structure) does not affect this bit.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 2 – SDCLKEN SD Clock Enable The peripheral stops the SD Clock when writing this bit to 0. SDCLK Frequency Select (SDCLKFSEL) can be changed when this bit is 0. Then, the peripheral maintains the same clock frequency until SDCLK is stopped (Stop at SDCLK=0). If Card Inserted (CARDINS) in PSR is cleared, this bit is also cleared.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.15 Timeout Control Register Name: Offset: Reset: Property: Bit TCR 0x2E 0x00 - 7 6 5 4 3 2 1 0 R/W R/W 0 R/W R/W 0 0 0 DTCVAL[3:0] Access Reset Bits 3:0 – DTCVAL[3:0] Data Timeout Counter Value This value determines the interval at which DAT line timeouts are detected. For more information about timeout generation, refer to Data Timeout Error (DATTEO) in EISTR.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.16 Software Reset Register Name: Offset: Reset: Property: Bit 7 SRR 0x2F 0x00 - 6 5 4 3 Access Reset 2 1 0 SWRSTDAT SWRSTCMD SWRSTALL R/W R/W R/W 0 0 0 Bit 2 – SWRSTDAT Software reset for DAT line Only part of a data circuit is reset. The DMA circuit is also reset. The following registers and bits are cleared by this bit: • Buffer Data Port Register 40.8.8 BDPR: BUFDATA is cleared and initialized. • Present State Register 40.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 0 1 Description Work Reset Bit 0 – SWRSTALL Software reset for All This reset affects the entire peripheral except the card detection circuit. During initialization, the peripheral must be reset by setting this bit to 1. This bit is automatically cleared to 0 when CA0R and CA1R are valid and the user can read them. If this bit is set to 1, the user should issue a reset command and reinitialize the card.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 1 Description Reset © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.17 Normal Interrupt Status Register Name: Offset: Reset: Property: Bit Access Reset Bit Access Reset NISTR 0x30 0x0000 - 15 14 13 12 11 10 9 8 ERRINT BOOTAR CINT R/W R/W R/W 0 0 0 7 6 5 4 3 2 1 0 CREM CINS BRDRDY BWRRDY DMAINT BLKGE TRFC CMDC R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 15 – ERRINT Error Interrupt If any of the bits in EISTR are set, then this bit is set.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... status is effective. If a non-zero value is set to INTPSEL, INT_A, INT_B or INT_C is used as device interrupts. This bit can only be set to 1 if NISTER.CREM is set to 1. An interrupt can only be generated if NISIER.CREM is set to 1. Value Description 0 No card interrupt 1 Card interrupt Bit 7 – CREM Card Removal Note: This register entry is specific to the SD/SDIO operation mode.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... This bit can only be set to 1 if NISTER.BWRRDY is set to 1. An interrupt can only be generated if NISIER.BWRRDY is set to 1. Writing this bit to 1 clears this bit. Value Description 0 Not ready to write buffer 1 Ready to write buffer Bit 3 – DMAINT DMA Interrupt This status is set if the peripheral detects the Host SDMA Buffer boundary during transfer. Refer to SDMA Buffer Boundary (BOUNDARY) in BSR.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... This bit is set at the falling edge of the DAT Line Active (DLACT) status. This interrupt is generated in two cases. The first is when the last data is written to the card as specified by the data length and the Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request (STPBGR) in BGCR and data transfers are completed.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.18 Error Interrupt Status Register Name: Offset: Reset: Property: Bit 15 EISTR 0x32 0x0000 - 14 13 Access Reset Bit Access Reset 12 11 10 9 8 BOOTAE ADMA ACMD R/W R/W R/W 0 0 0 7 6 5 4 3 2 1 0 CURLIM DATEND DATCRC DATTEO CMDIDX CMDEND CMDCRC CMDTEO R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 12 – BOOTAE Boot Acknowledge Error Note: This register entry is specific to the e.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Writing this bit to 1 clears this bit. Value Description 0 No error 1 Error Bit 7 – CURLIM Current Limit Error By setting SD Bus Power (SDBPWR) in PCR, the peripheral is requested to supply power for the SD Bus. The peripheral is protected from an illegal card by stopping power supply to the card, in which case this bit indicates a failure status. Reading 1 means the peripheral is not supplying power to the card due to some failure.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 0 1 Description No error Error Bit 3 – CMDIDX Command Index Error This bit is set to 1 if a Command Index error occurs in the command response. This bit can only be set to 1 if EISTER.CMDIDX is set to 1. An interrupt can only be generated if EISIER.CMDIDX is set to 1. Writing this bit to 1 clears this bit.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... ...........continued CMDCRC CMDTEO Types of error 1 1 CMD line conflict © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.19 Normal Interrupt Status Enable Register: e.MMC Name: Offset: Reset: Property: Bit 15 Access Reset Bit Access Reset NISTER 0x34 0x0000 - 14 13 12 11 10 9 8 BOOTAR CINT R/W R/W 0 0 7 6 5 4 3 2 1 0 CREM CINS BRDRDY BWRRDY DMAINT BLKGE TRFC CMDC R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 14 – BOOTAR Boot Acknowledge Received Status Enable Note: This register entry is specific to the e.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 0 1 Name MASKED ENABLED Description The BWRRDY status flag in NISTR is masked. The BWRRDY status flag in NISTR is enabled. Bit 3 – DMAINT DMA Interrupt Status Enable Value Name Description 0 MASKED The DMAINT status flag in NISTR is masked. 1 ENABLED The DMAINT status flag in NISTR is enabled. Bit 2 – BLKGE Block Gap Event Status Enable Value Name Description 0 MASKED The BLKGE status flag in NISTR is masked.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 4 – DATTEO Data Timeout Error Status Enable Value Name Description 0 MASKED The DATTEO status flag in EISTR is masked. 1 ENABLED The DATTEO status flag in EISTR is enabled. Bit 3 – CMDIDX Command Index Error Status Enable Value Name Description 0 MASKED The CMDIDX status flag in EISTR is masked. 1 ENABLED The CMDIDX status flag in EISTR is enabled.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.21 Normal Interrupt Signal Enable Register Name: Offset: Reset: Property: Bit 15 Access Reset Bit Access Reset NISIER 0x38 0x0000 - 14 13 12 11 10 9 8 BOOTAR CINT R/W R/W 0 0 7 6 5 4 3 2 1 0 CREM CINS BRDRDY BWRRDY DMAINT BLKGE TRFC CMDC R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 14 – BOOTAR Boot Acknowledge Received Signal Enable Note: This register entry is specific to the e.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 1 Name ENABLED Description An interrupt is generated when NISTR.BRDRDY is set. Bit 4 – BWRRDY Buffer Write Ready Signal Enable Value Name Description 0 MASKED No interrupt is generated when NISTR.BWRRDY is set. 1 ENABLED An interrupt is generated when NISTR.BWRRDY is set. Bit 3 – DMAINT DMA Interrupt Signal Enable Value Name Description 0 MASKED No interrupt is generated when NISTR.DMAINT is set.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 4 – DATTEO Data Timeout Error Signal Enable Value Name Description 0 MASKED No interrupt is generated when EISTR.DATTEO is set. 1 ENABLED An interrupt is generated when EISTR.DATTEO is set. Bit 3 – CMDIDX Command Index Error Signal Enable Value Name Description 0 MASKED No interrupt is generated when EISTR.CMDIDX is set. 1 ENABLED An interrupt is generated when EISTR.CMDIDX is set.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.23 Auto CMD Error Status Register Name: Offset: Reset: Property: Bit ACESR 0x3C 0x0000 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit CMDNI ACMDIDX ACMDEND ACMDCRC ACMDTEO ACMD12NE Access R R R R R R Reset 0 0 0 0 0 0 Bit 7 – CMDNI Command Not Issued by Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (ACESR[4:1]).
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... ...........continued ACMDCRC ACMDTEO Types of error 1 0 Response CRC error 1 1 CMD line conflict Bit 0 – ACMD12NE Auto CMD12 Not Executed If a memory multiple block data transfer is not started due to a command error, this bit is not set to 1 because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the peripheral cannot issue Auto CMD12 to stop a memory multiple block data transfer due to some error.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.24 Host Control 2 Register: e.MMC Name: Offset: Reset: Property: HC2R - EMMC 0x3E 0x0000 - Note: The content of the HC2R register is depending on the mode. This description is for e.MMC mode. For SD/SDIO mode, see 40.8.25 HC2R - DEFAULT.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 6 – EXTUN Execute Tuning This bit is set to 1 to start the tuning procedure and is automatically cleared when the tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select (SCLKSEL). The tuning procedure is aborted by writing 0. Refer to Figure 2.29 in the “SD Host Controller Simplified Specification V3.00” .
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.25 Host Control 2 Register: SD/SDIO Name: Offset: Reset: Property: HC2R - DEFAULT 0x3E 0x0000 - Note: The content of the HC2R register is depending on the mode. This description is for SD/SDIO mode. For e.MMC mode, see 40.8.24 HC2R - EMMC.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... tuning sequence in a short time. Changing this bit is not allowed while the peripheral is receiving a response or a read data block. Refer to Figure 2.29 in the “SD Host Controller Simplified Specification V3.00” . Value Description 0 The fixed clock is used to sample data. 1 The tuned clock is used to sample data.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 0 1 2 3 4 Name SDR12 SDR25 SDR50 SDR104 DDR50 Description UHS SDR12 Mode UHS SDR25 Mode UHS SDR50 Mode UHS SDR104 Mode UHS DDR50 Mode Note: This field is effective only if MC1R.DDR is set to 0. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.26 Capabilities 0 Register Name: Offset: Reset: Property: CA0R 0x40 0x27E80080 - Note: The Capabilities 0 Register is not supposed to be written by the user.
PAGE 1371
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 28 – SB64SUP 64-Bit System Bus Support This bit indicates if the peripheral supports the 64-bit Address Descriptor mode and is connected to the 64-bit address system bus. Value Description 0 64-bit address bus not supported 1 64-bit address bus supported Bit 26 – V18VSUP Voltage Support 1.8V Value Description 0 1.8V Voltage supply not supported 1 1.8V Voltage supply supported Bit 25 – V30VSUP Voltage Support 3.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 19 – ADMA2SUP ADMA2 Support This bit indicates whether the peripheral is capable of using ADMA2. Value Description 0 ADMA2 not supported 1 ADMA2 supported Bit 18 – ED8SUP 8-Bit Support for Embedded Device This bit indicates whether the peripheral is capable of using the 8-bit Bus Width mode.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.27 Capabilities 1 Register Name: Offset: Reset: Property: CA1R 0x44 0x00000070 - Note: The Capabilities 1 Register is not supposed to be written by the user.
PAGE 1374
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 0 Description Driver type D is not supported. Bit 5 – DRVCSUP Driver Type C Support Value Description 0 Driver type C is not supported. Bit 4 – DRVASUP Driver Type A Support Value Description 0 Driver type A is not supported. Bit 2 – DDR50SUP DDR50 Support Value Description 0 DDR50 mode is not supported. Bit 1 – SDR104SUP SDR104 Support Value Description 0 SDR104 mode is not supported. 1 SDR104 mode is supported.
PAGE 1375
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
PAGE 1376
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.29 Force Event Register for Auto CMD Error Status Name: Offset: Reset: Property: Bit FERACES 0x50 0x0000 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit CMDNI ACMDIDX ACMDEND ACMDCRC ACMDTEO ACMD12NE Access W W W W W W Reset 0 0 0 0 0 0 Bit 7 – CMDNI Force Event for Command Not Issued by Auto CMD12 Error For testing purposes, the user can write this bit to 1 to rise the CMDNI status flag in ACESR.
PAGE 1377
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
PAGE 1378
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 2 – CMDEND Force Event for Command End Bit Error For testing purposes, the user can write this bit to 1 to rise the CDMEND status flag in EISTR. Writing this bit to 0 has no effect. Bit 1 – CMDCRC Force Event for Command CRC Error For testing purposes, the user can write this bit to 1 to rise the CMDCRC status flag in EISTR. Writing this bit to 0 has no effect.
PAGE 1379
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.31 ADMA Error Status Register Name: Offset: Reset: Property: Bit 7 AESR 0x54 0x00 - 6 5 4 3 2 1 LMIS 0 ERRST[1:0] Access R R R Reset 0 0 0 Bit 2 – LMIS ADMA Length Mismatch Error This error occurs in the following two cases: • While Block Count Enable (BCEN) is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count (BLKCNT) and Transfer Block Size (BLKSIZE).
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.33 Preset Value Register Name: Offset: Reset: Property: PVR 0x60 + n*0x02 [n=0..7] 0x0000 Read/Write One of the Preset Value Registers is effective based on the selected bus speed mode. The table below defines the conditions to select one of the PVRs. Table 40-3.
PAGE 1382
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Bit 15 14 13 12 11 10 CLKGSEL Access Reset Bit 7 6 5 4 3 9 8 SDCLKFSEL[9:8] R/W R/W R/W 0 0 0 2 1 0 SDCLKFSEL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 10 – CLKGSEL Clock Generator Select Refer to CGGSEL in CCR. Bits 9:0 – SDCLKFSEL[9:0] SDCLK Frequency Select Refer to SDCLKFSEL in CCR. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.34 Slot Interrupt Status Register Name: Offset: Reset: Property: Bit SISR 0xFC 0x0000 - 15 14 13 12 11 10 9 8 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Access Reset INTSSL[7:0] Bits 7:0 – INTSSL[7:0] Interrupt Signal for Each Slot These status bits indicate the logical OR of Interrupt Signals and WakeUp Signal for each peripheral instance in the device.
PAGE 1384
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.35 Host Controller Version Register Name: Offset: Reset: Property: HCVR 0xFE 0x1802 - Bit 15 14 13 12 11 10 9 8 Access R R R R Reset 0 0 R R R R 0 1 1 0 0 0 Bit 7 6 5 4 3 2 1 0 VVER[7:0] SVER[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 1 0 Bits 15:8 – VVER[7:0] Vendor Version Number Reserved. Value subject to change. No functionality associated.
PAGE 1385
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
PAGE 1386
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.37 e.MMC Control 1 Register Name: Offset: Reset: Property: Bit Access Reset MC1R 0x204 0x00 R/W 7 6 5 4 3 2 1 0 FCD RSTN BOOTA OPD DDR R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 CMDTYP[1:0] Bit 7 – FCD e.MMC Force Card Detect When using e.MMC, the user can set this bit to 1 to bypass the card detection procedure using the CD signal. Value Name Description 0 DISABLED e.MMC Forced Card Detect is disabled.
PAGE 1387
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... Value 1 Description High Speed DDR is selected. Note: The clock divider (DIV) in CCR must be set to a value different from 0 when HSEN is 1. Bits 1:0 – CMDTYP[1:0] e.MMC Command Type Value Name Description 0 NORMAL The command is not an e.MMC specific command. 1 WAITIRQ This bit must be set to 1 when the e.MMC is in Interrupt mode (CMD40). Refer to “Interrupt Mode” in the “Embedded MultiMedia Card (e.MMC) Electrical Standard 4.51” .
PAGE 1388
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.38 e.MMC Control 2 Register Name: Offset: Reset: Property: Bit 7 MC2R 0x205 0x00 - 6 5 4 3 2 1 0 ABOOT SRESP Access W W Reset 0 0 Bit 1 – ABOOT e.MMC Abort Boot This bit is used to exit from Boot mode. Writing this bit to 1 exits the Boot Operation mode. Writing 0 is ignored. Bit 0 – SRESP e.MMC Abort Wait IRQ This bit is used to exit from the Interrupt mode.
PAGE 1389
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.39 AHB Control Register Name: Offset: Reset: Property: Bit ACR 0x208 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 BMAX[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – BMAX[1:0] AHB Maximum Burst This field selects the maximum burst size in case of DMA transfer.
PAGE 1390
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
PAGE 1391
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.
PAGE 1392
SAM D5x/E5x Family Data Sheet SD/MMC Host Controller ... 40.8.42 Debug Register Name: Offset: Reset: Property: Bit DBGR 0x234 0x00 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit NIDBG Access R/W Reset 0 Bit 0 – NIDBG Non-Intrusive Debug Value Name Description 0 DISABLED Reading the BDPR via debugger increments the dual port RAM read pointer. 1 ENABLED Reading the BDPR via debugger does not increment the dual port RAM read pointer. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41. 41.1 CCL – Configurable Custom Logic Overview The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device pins, to events, or to other internal peripherals. This allows the user to eliminate logic gates for simple glue logic functions on the PCB. Each LookUp Table (LUT) consists of three inputs, a truth table, an optional synchronizer/filter, and an optional edge detector.
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SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.3 Block Diagram Figure 41-1.
PAGE 1395
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.5.2 Power Management This peripheral can continue to operate in any Sleep mode where its source clock is running. Events connected to the event system can trigger other operations in the system without exiting Sleep modes. Related Links 18. PM – Power Manager 41.5.
PAGE 1396
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.5.9 Analog Connections Not applicable. 41.6 Functional Description 41.6.1 Principle of Operation Configurable Custom Logic (CCL) is a programmable logic block that can use the device port pins, internal peripherals, and the internal Event System as both input and output channels. The CCL can serve as glue logic between the device and external devices.
PAGE 1397
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Figure 41-2. Truth Table Output Value Selection LUT TRUTH[0] TRUTH[1] TRUTH[2] TRUTH[3] TRUTH[4] TRUTH[5] TRUTH[6] TRUTH[7] OUT LUTCTRL (ENABLE) IN[2:0] Table 41-1. Truth Table of LUT IN[2] IN[1] IN[0] OUT 0 0 0 TRUTH[0] 0 0 1 TRUTH[1] 0 1 0 TRUTH[2] 0 1 1 TRUTH[3] 1 0 0 TRUTH[4] 1 0 1 TRUTH[5] 1 1 0 TRUTH[6] 1 1 1 TRUTH[7] 41.6.2.
PAGE 1398
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Figure 41-3. Masked Input Selection Internal Feedback Inputs (FEEDBACK) When selected (LUTCTRLx.INSELy=FEEDBACK), the Sequential (SEQ) output is used as input for the corresponding LUT. The output from an internal sequential sub-module can be used as input source for the LUT, see figure below for an example for LUT0 and LUT1.
PAGE 1399
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Figure 41-5. Linked LUT Input Selection LUT0 SEQ 0 CTRL (ENABLE) LUT1 LUT2 SEQ 1 CTRL (ENABLE) LUT3 LUT(2n – 2) SEQ n CTRL (ENABLE) LUT(2n-1) Internal Events Inputs Selection (EVENT) Asynchronous events from the Event System can be used as input selection, as shown in the below image. For each LUT, one event input line is available and can be selected on each LUT input. Before enabling the event selection by writing LUTCTRLx.
PAGE 1400
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Figure 41-6. Event Input Selection I/O Pin Inputs (IO) When the IO pin is selected as LUT input (LUTCTRLx.INSELy=IO), the corresponding LUT input will be connected to the pin, as shown in the figure below. Figure 41-7. I/O Pin Input Selection Analog Comparator Inputs (AC) The AC outputs can be used as input source for the LUT (LUTCTRLx.INSELy=AC).
PAGE 1401
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Figure 41-8. AC Input Selection Timer/Counter Inputs (TC) The TC waveform output WO[0] can be used as input source for the LUT (LUTCTRLx.INSELy=TC). Only consecutive instances of the TC, i.e. TCx and the subsequent TC(x+1), are available as default and alternative TC selections (e.g., TC0 and TC1 are sources for LUT0, TC1 and TC2 are sources for LUT1, etc). See the figure below for an example for LUT0.
PAGE 1402
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Timer/Counter for Control Application Inputs (TCC) The TCC waveform outputs can be used as input source for the LUT. Only WO[2:0] outputs can be selected and routed to the respective LUT input (i.e., IN0 is connected to WO0, IN1 to WO1, and IN2 to WO2), as shown in the figure below. Note: The TCC selection for each LUT follows the formula: IN � � = �� % ��C_Instance_Number Where N represents the LUT number.
PAGE 1403
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.6.2.5 Filter By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short glitches when the inputs change value. These glitches can be removed by clocking through filters, if demanded by application needs. The Filter Selection bits in LUT Control register (LUTCTRLx.FILTSEL) define the synchronizer or digital filter options.
PAGE 1404
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Gated D Flip-Flop (DFF) When the DFF is selected, the D-input is driven by the even LUT output (LUT0 and LUT2), and the Ginput is driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 41-14. Figure 41-14. D Flip Flop When the even LUT is disabled (LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the flip-flop is asynchronously cleared. The reset command (R) is kept enabled for one APB clock cycle.
PAGE 1405
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Gated D-Latch (DLATCH) When the DLATCH is selected, the D-input is driven by the even LUT output (LUT0 and LUT2), and the G-input is driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 41-14. Figure 41-16. D-Latch even LUT D odd LUT G Q OUT When the even LUT is disabled (LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the latch output will be cleared. The G-input is forced enabled for one more APB clock cycle, and the D-input to zero.
PAGE 1406
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic The CCL can take the following actions on an input event: • INSELx: The event is used as input for the TRUTH table. For further details refer to 41.5.6 Events. Writing a '1' to the LUT Control Event Input Enable bit (LUTCTRL.LUTEI) enables the corresponding action on input event. Writing a '0' to this bit disables the corresponding action on input event. Related Links 31. EVSYS – Event System 41.6.
PAGE 1407
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.7 Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 RUNSTDBY ENABLE SWRST 0x01 ... Reserved 0x03 0x04 SEQCTRL0 7:0 SEQSEL[3:0] 0x05 SEQCTRL1 7:0 SEQSEL[3:0] 0x06 ...
PAGE 1408
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.8.1 Control Name: Offset: Reset: Property: Bit 7 Access Reset CTRL 0x00 0x00 PAC Write-Protection 6 5 4 3 2 1 0 RUNSTDBY ENABLE SWRST R/W R/W W 0 0 0 Bit 6 – RUNSTDBY Run in Standby This bit indicates if the GCLK_CCL clock must be kept running in standby mode. The setting is ignored for configurations where the generic clock is not required. For details refer to 41.6.4 Sleep Mode Operation.
PAGE 1409
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.8.2 Sequential Control x Name: Offset: Reset: Property: Bit 7 SEQCTRL 0x04 + n*0x01 [n=0..
PAGE 1410
SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic 41.8.3 LUT Control x Name: Offset: Reset: Property: Bit LUTCTRL 0x08 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet CCL – Configurable Custom Logic Bits 5:4 – FILTSEL[1:0] Filter Selection These bits select the LUT output filter options: Filter Selection Value Name Description 0x0 DISABLE Filter disabled 0x1 SYNCH Synchronizer enabled 0x2 FILTER Filter enabled 0x3 Reserved Bit 1 – ENABLE LUT Enable Value Description 0 The LUT is disabled. 1 The LUT is enabled.
PAGE 1412
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42. AES – Advanced Encryption Standard 42.1 Overview The Advanced Encryption Standard peripheral (AES) provides a means for symmetric-key encryption of 128-bit blocks, in compliance to NIST specifications. A symmetric-key algorithm requires the same key for both encryption and decryption. Different key sizes are supported.
PAGE 1413
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard Block Diagram ENCRYPTION PLAINTEXT CIPHERTEXT ADD ROUND KEY ADD ROUND KEY SUBBYTES INV SHIFT ROWS SHIFT ROWS Nr-1 rounds MIX COLUMNS ADD ROUND KEY DECRYPTION ROUND ENCRYPTION ROUND Figure 42-1. AES Block Diagram DECRYPTION INV SUBBYTES Nr-1 rounds ADD ROUND KEY INV MIX COLUMNS SUBBYTES INV SHIFT ROWS FINAL ROUND FINAL ROUND 42.
PAGE 1414
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.4 Signal Description Not applicable. 42.5 Product Dependencies In order to use this AES module, other parts of the system must be configured correctly, as described below. 42.5.1 I/O Lines Not applicable. 42.5.2 Power Management The AES will continue to operate in Standby sleep mode, if it's source clock is running. The AES interrupts can be used to wake up the device from Standby sleep mode.
PAGE 1415
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.5.7 Debug Operation When the CPU is halted in debug mode, the AES module continues normal operation. If the AES module is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The AES module can be forced to halt operation during debugging. 42.5.
PAGE 1416
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard where Nr is the number of rounds, depending on the key length. 42.6.2 Basic Operation 42.6.2.1 Initialization The following register is enable-protected: • Control A (CTRLA) Enable-protection is denoted by the Enable-Protected property in the register description. 42.6.2.2 Enabling, Disabling, and Resetting The AES module is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE).
PAGE 1417
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard read is performed is indicated by the Data Pointer field in the Data Buffer Pointer register (DATABUFPTR). This field is incremented by one or wrapped by hardware when a read from the DATA register address is performed. This field can also be programmed, giving the user direct control over which output buffer register to read from.
PAGE 1418
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 3. Last Output Data Mode (LOD) This mode is used to generate message authentication code (MAC) on data in CCM mode of operation. The CCM mode combines counter mode for encryption and CBC-MAC generation for authentication. When LOD is disabled in CCM mode then counter mode of encryption is performed on the input data block. When LOD is enabled in CCM mode then CBC-MAC generation is performed.
PAGE 1419
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard • Type 3: Add a random number of clock cycles to data processing, subject to a maximum of 11/13/15 clock cycles for key sizes of 128/192/256 bits • Type 4: Add random spurious power consumption during data processing By default, all countermeasures are enabled. One or more of the countermeasures can be disabled by programming the Countermeasure Type field in the Control A (CTRLA.CTYPE) register.
PAGE 1420
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard Counter 0 Incr32 CIPH(K) Counter 1 Incr32 CIPH(K) Plaintext 1 Encryption GF128Mult(H) + Counter 2 CIPH(K) Plaintext 2 + Ciphertext 1 Ciphertext 2 + + GF128Mult(H) GF128Mult(H) Len (A) || Len (C) Auth Data 1 + GF128Mult(H) + Auth Tag Authentication © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.6.3.1 GCM Operation 42.6.3.1.1 Hashkey Generation • Configure CTRLA register as follows: 1. CTRLA.STARTMODE as Manual (Auto for DMAC) 2. CTRLA.CIPHER as Encryption 3. CTRLA.KEYSIZE as per the key used 4. CTRLA.AESMODE as ECB 5. CTRLA.CTYPE as per the countermeasures required. • Set CTRLA.ENABLE • Write zero to CIPLEN reg. • Write the key in KEYWORD register • Write the zeros to DATA reg • Set CTRLB.Start. • Wait for INTFLAG.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard GHASH AUTHDAT + GF128Mult(H) GHASH 42.6.3.1.3 Plain text Processing • • • • • • • • • • • • • • • • • • Set CTRLB.NEWMSG for the new set of plain text processing. Load CIPLEN reg. Load (J0+1) in INTVECT register.
PAGE 1423
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard • • • • • • • • • • AES Hardware generates output in DATA register. Intermediate GHASH is stored in GHASH register and Cipher Text available in DATA register. Continue 3 to 5 till the input of plain text to get the cipher text and the Hash keys. At the last input, set CTRLB.EOM. Write last in-data to DATA reg. Wait for INTFLAG.ENCCMP to be set. AES Hardware generates output in DATA register and final Hash key in GHASH register.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.7 Offset Register Summary Name Bit Pos. 7:0 CFBS[2:0] 15:8 XORKEY AESMODE[2:0] KEYGEN LOD STARTMODE ENABLE CIPHER SWRST KEYSIZE[1:0] 0x00 CTRLA 0x04 CTRLB 7:0 NEWMSG START 0x05 INTENCLR 7:0 GFMCMP ENCCMP 0x06 INTENSET 7:0 GFMCMP ENCCMP 0x07 INTFLAG 7:0 GFMCMP ENCCMP 0x08 DATABUFPTR 7:0 0x09 DBGCTRL 7:0 23:16 CTYPE[3:0] 31:24 GFMUL EOM INDATAPTR[1:0] DBGRUN 0x0A ...
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard ...........continued Offset 28 Name KEYWORD7 Bit Pos. 7:0 KEYWORD[7:0] 15:8 KEYWORD[15:8] 23:16 KEYWORD[23:16] 31:24 KEYWORD[31:24] 7:0 DATA[7:0] 0x2C ...
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard ...........continued Offset 0x68 0x6C 0x70 0x74 0x78 Name HASHKEY3 GHASH0 GHASH1 GHASH2 GHASH3 Bit Pos.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard Bit 12 – LOD Last Output Data Mode Value Description 0 No effect 1 Start encryption in Last Output Data mode Bit 11 – STARTMODE Start Mode Select Value Name Description 0 Manual Mode Start Encryption / Decryption in Manual mode 1 Auto Mode Start Encryption / Decryption in Auto mode Bit 10 – CIPHER Cipher Mode Select Value Description 0 Decryption 1 Encryption Bits 9:8 – KEYSIZE[1:0] Encryption Key Size Value Name Description 0 128-bit Key 128-
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard Value 1 Description The peripheral is enabled Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the AES module to their initial state, and the module will be disabled. Writing a '1' to SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.2 Control B Name: Offset: Reset: Property: Bit 7 CTRLB 0x04 0x00 PAC Write-Protection 6 5 4 3 2 1 0 GFMUL EOM NEWMSG START R/W R/W R/W R/W 0 0 0 0 Access Reset Bit 3 – GFMUL GF Multiplication This bit is applicable only to GCM mode. Value Description 0 No action 1 Setting this bit calculates GF multiplication with data buffer content and hashkey register content.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.3 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x05 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.4 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x06 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.5 Interrupt Flag Status and Clear Name: Offset: Reset: Bit 7 INTFLAG 0x07 0x00 6 5 4 3 Access Reset 2 1 0 GFMCMP ENCCMP R/W R/W 0 0 Bit 1 – GFMCMP GF Multiplication Complete This flag is cleared by writing a '1' to it. This flag is set when GHASH value is available on the Galois Hash Registers (GHASHx) in GCM mode. Writing a '0' to this bit has no effect. This flag is also automatically cleared in the following cases.
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.6 Data Buffer Pointer Name: Offset: Reset: Property: Bit 7 DATABUFPTR 0x08 0x00 PAC Write-Protection 6 5 4 3 2 1 0 INDATAPTR[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – INDATAPTR[1:0] Input Data Pointer Writing to this field changes the value of the input data pointer, which determines which of the four data registers is written to/read from when the next write/read to the DATA register address is performed.
PAGE 1435
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.7 Debug Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x09 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access W Reset 0 Bit 0 – DBGRUN Debug Run Writing a '0' to this bit causes the AES to halt during debug mode. Writing a '1' to this bit allows the AES to continue normal operation during debug mode. This bit can only be changed while the AES is disabled. © 2019 Microchip Technology Inc.
PAGE 1436
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.8 Keyword Name: Offset: Reset: Property: KEYWORD 0x0C + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.
PAGE 1438
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.10 Initialization Vector Register Name: Offset: Reset: Property: INTVECTV 0x3C + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.11 Hash Key (GCM mode only) Name: Offset: Reset: Property: Bit HASHKEY 0x5C + n*0x04 [n=0..
PAGE 1440
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.12 Galois Hash (GCM mode only) Name: Offset: Reset: Property: Bit GHASH 0x6C + n*0x04 [n=0..
PAGE 1441
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.
PAGE 1442
SAM D5x/E5x Family Data Sheet AES – Advanced Encryption Standard 42.8.
PAGE 1443
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43. Public Key Cryptography Controller (PUKCC) 43.1 Overview The Public Key Cryptography Controller (PUKCC) processes public key cryptography algorithm calculus in both GF(p) and GF(2n) fields. The PUKCL (PUblic Key Cryptography Library) is stored in ROM inside the device. This library can be used in applications to access features of PUKCC.
PAGE 1444
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.2.6 Events Not applicable. 43.3 Functional Description 43.3.1 Public Key Cryptography Library (PUKCL) Application Programming Interface (API) The Public Key Cryptography Controller (PUKCC) is a peripheral that can be used to accelerate public key cryptography, and processes public key cryptography algorithm calculus in both Prime field (GF(p)) and Binary field (GF(2n)).
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) // Clear contents of PUKCLParam memset(&PUKCLParam, 0, sizeof(PUKCL_PARAM)); pvPUKCLParam = &PUKCLParam; vPUKCL_Process(SelfTest, pvPUKCLParam); } // In while ; } while ; } while ; } while ; } case of error, loop here (PUKCL(u2Status) != PUKCL_OK) { (pvPUKCLParam->P.PUKCL_SelfTest.u4Version != PUKCL_VERSION) { (pvPUKCLParam->P.PUKCL_SelfTest.u4CheckNum1 != 0x6E70DDD2) { (pvPUKCLParam->P.PUKCL_SelfTest.
PAGE 1446
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) _PUKCL_SELFTEST _PUKCL_SMULT _PUKCL_SQUARE _PUKCL_SWAP PUKCL_SelfTest; PUKCL_Smult; PUKCL_Square; PUKCL_Swap; // ECC _PUKCL_ZPECCADD _PUKCL_ZPECCDBL _PUKCL_ZPECCADDSUB _PUKCL_ZPECCMUL _PUKCL_ZPECDSAGENERATE _PUKCL_ZPECDSAVERIFY _PUKCL_ZPECDSAQUICKVERIFY _PUKCL_ZPECCQUICKDUALMUL _PUKCL_ZPECCONVPROJTOAFFINE _PUKCL_ZPECCONVAFFINETOPROJECTIVE _PUKCL_ZPECRANDOMIZECOORDINATE _PUKCL_ZPECPOINTISONCURVE PUKCL_ZpEccAdd; PUKCL_ZpEccDbl; PUKCL_
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter Type Direction Location Data Length Before Executing the Service After Executing the Service u2Status (see 43.3.3.6 Return Codes) u2 I/O – – – Output Status Reserved u2 – – – – – Reserved u4 – – – – – The Specific field in the PUKCL_HEADER structure is another structure named PUKCL_STATUS. The following table describes this structure.
PAGE 1448
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) To check whether the version returned by the PUKCL is correct, the following code can be used. while (pvPUKCLParam->P.PUKCL_SelfTest.u4Version != PUKCL_VERSION); In a similar way, other returns can also be accessed. 43.3.3.3 Parameter Passing (Special Considerations) Most of the PUKCL services work with memory area and accept pointers and lengths as parameters to define input and output areas.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Figure 43-1. Return Code Status Decoding The following table shows how the severity indicators should be decoded. Table 43-3.
PAGE 1450
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Please note the following rules about return codes: • A status value indicating a severe error, means that an expected operation has not been executed or has been corrupted. Therefore, the result of such an operation should never be used. • A status value indicating a warning should be looked at precisely, as the expected correctness of the result cannot be guaranteed.
PAGE 1451
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) { // // // // } The Library version is available in PUKCL_SelfTest(u4Version) The PUKCL version is available in PUKCL_SelfTest(u4PUKCCVersion) 43.3.4.1.6 Returned Values The expected u4Version value depends on the version of PUKCL being used, and the u4PUKCCVersion value depends on the version of PUKCC being used. The expected u4CheckNum1 value is 0x6e70ddd2 and the expected one for u4CheckNum2 is 0x25c8d64f.
PAGE 1452
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) } else // Manage the error 43.3.4.2.6 Status Returned Values Table 43-8. ClearFlags Service Return Codes Returned Status Importance Meaning PUKCL_OK – Service functioned correctly. 43.3.4.3 Swap 43.3.4.3.1 Purpose This service performs swapping of two buffers. 43.3.4.3.2 How to Use the Service 43.3.4.3.3 Description This service swaps two buffers, X and Y, of the same size in memory.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • {nu1XBase, u2XLength} overlaps {nu1YBase,u2YLength} 43.3.4.3.7 Status Returned Values Table 43-10. Swap Service Return Codes Returned status Importance Meaning PUKCL_OK – Service functioned correctly 43.3.4.4 Fill 43.3.4.4.1 Purpose This service performs a memory fill operation, with a given 32-bit constant. 43.3.4.4.2 How to Use the Service 43.3.4.4.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.4.4.7 Status Returned Values Table 43-12. Fill Service Return Codes Returned Status Importance Meaning PUKCL_OK – Service functioned correctly. 43.3.4.5 Fast Copy/Clear 43.3.4.5.1 Purpose This service performs a copy from a memory area to another or a memory area clear. 43.3.4.5.2 How to Use the Service 43.3.4.5.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) // vPUKCL_Process() is a macro command, which populates the service name // and then calls the library... vPUKCL_Process(FastCopy,pvPUKCLParam); if (PUKCL(u2Status) == PUKCL_OK) { ... } else // Manage the error 43.3.4.5.6 Constraints The parameter placements that are not allowed are are as follows. If nu1XBase equals zero, no checks are made on nu1XBase (fixed) and u2XLength (unused).
PAGE 1456
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Important: If the condition is verified, the length of R must be greater or equal to the length of X. 43.3.4.6.4 Parameters Definition This service can easily be accessed through the use of the PUKCL_CondCopy() and PUKCL() macros. Table 43-15.
PAGE 1457
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) // Condition Option PUKCL(u2Options) = ...; // Initialize parameters PUKCL_CondCopy(nu1XBase) = ; the R number>; of the X number>; of the R number>; // vPUKCL_Process() is a macro command, which populates the service name // and then calls the library...
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.4.7.2 How to Use the Service 43.3.4.7.3 Description This service processes the following operation (if not computing a modular reduction of the result): R = [Z] ± (MulValue × X + CarryOperand) Or (if computing a modular reduction of the result): R = ([Z] ± (MulValue × X + CarryOperand))mod N The service name for this operation is Smult.
PAGE 1459
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Important: The result buffer R must first be padded with zero bytes until its length is sufficient to perform the reduction (2*u2ModLength + 8) to be used by the Modular Reduction service as an input parameter. The result of the reduction is written in the area X pointed by {nu1XBase, u2ModLength + 4}.
PAGE 1460
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter u4MulValue Type Direction u4 I Location Data Length Before Executing the Service After Executing the Service – – Value of MulValue Value of MulValue untouched Note: 1. If a reduction option is specified, the area X will be, if necessary, extended to u2ModLength + 4 bytes. 2. If Smult is without reduction, X is untouched. If Smult is with reduction, X is filled with the final result. 3.
PAGE 1461
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.4.7.6 Code Example PUKCL_PARAM PUKCLParam; PPUKCL_PARAM pvPUKCLParam = &PUKCLParam; // Gf2n and CarryIn shall be beforehand filled (with zero or one) PUKCL(Specific).Gf2n = ...; PUKCL(Specific).CarryIn = ...; PUKCL(u2Options) =...
PAGE 1462
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) R = (Z ± (MulValue × X + CarryOperand))mod BRLength Table 43-20.
PAGE 1463
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Important: This service works only with integers. 43.3.4.8.2 How to Use the Service 43.3.4.8.3 Description This service accepts two numbers in classical arithmetic in input and performs a comparison, virtually subtracting (X + CarryIn) from Y: CompareGetFlags (Y - (X + CarryIn)) The numbers X and Y are untouched but the resulting flags CarryOut and the Zero Bit are filled.
PAGE 1464
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) // vPUKCL_Process() is a macro command, // and then calls the library... vPUKCL_Process(Comp,pvPUKCLParam); if (PUKCL(u2Status) == PUKCL_OK) { // The COMPARE has been executed correctly // CarryOut, Zero ... are available ... = PUKCL(Specific).CarryOut; ... = PUKCL(Specific).Zero; } else // Manage the error 43.3.4.8.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • CarryOperand (provided through the Carry Options and Carry values) Important: Even if neither accumulation nor subtraction is specified, the nu1ZBase must always be filled and point to a Crypto RAM space. It this case, nu1ZBase can point to the same space as the nu1RBase. If using the big modular reduction option, the Multiply operation is followed by a reduction (see 43.3.5.1 Modular Reduction).
PAGE 1466
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1467
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) The following table shows all of the necessary parameters for the Full Multiply option. When the Addition or Subtraction option is not chosen, it is not necessary to fill in the nu1ZBase parameter. Table 43-26.
PAGE 1468
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.4.9.7 Important Considerations for Modular Reduction of a Fmult Computation Result Note: Additional options are available through the use of a modular reduction to be executed at the end of this operation. Some important considerations have to be taken into account concerning the length of resulting operands to get a mathematically correct result.
PAGE 1469
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Multiplication without Accumulation or Subtraction In the case the options bits specify that either an Accumulation or a subtraction should be performed, this service performs the following operation: R = (X × Y + CarryOperand)mod BXLength + YLength Table 43-28.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) The service name for this operation is Square.
PAGE 1471
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1472
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) PUKCL(u2Options) = SET_MULTIPLIEROPTION(PUKCL_SQUARE_ADD) | SET_CARRYOPTION(ADD_CARRY) | PUKCL_REDMOD_REDUCTION | PUKCL_REDMOD_USING_FASTRED; The following table lists all of the necessary parameters for the Square option. When the Addition or Subtraction option is not chosen it is not necessary to fill in the nu1ZBase parameter. Table 43-31.
PAGE 1473
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.4.10.8 Constraints When the options only indicate a square, the constraints involving nu1ZBase are not checked.
PAGE 1474
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Option AND CARRYOPTIONS CarryOperand Resulting Operation SET_CARRYOPTION(ADD_1) 1 R = X2 + 1 SET_CARRYOPTION(SUB_1) -1 R = X2 - 1 SET_CARRYOPTION(ADD_2) 2 R = X2 + 2 43.3.4.10.10 Status Returned Values Table 43-34. Square Service Return Codes Returned status Importance Meaning PUKCL_OK – Service functioned correctly 43.3.4.11 Integral (Euclidean) Division 43.3.4.11.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • R (pointed by {nu1RBase,u2ModLength}) to contain the calculated Remainder. The service name for this operation is Div. 43.3.4.11.4 Parameters Definition Table 43-35. Div Service Parameters Parameter Type Dir.
PAGE 1476
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Note: The parameter Num must have its most significant 32-bit word cleared to zero. The length u2NumLength is the length of Num including this zero word. One additional word is used on the LSB side of the Num parameter, this word is restored at the end of the calculus. As a consequence the parameter nu1NumBase must never been at the beginning of the Crypto RAM, i.e., ensure that nu1NumBase ≥ + 4 bytes.
PAGE 1477
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.4.11.7 Status Returned Values Table 43-36. Div Service Return Codes Returned Status Importance Meaning PUKCL_OK – PUKCL_DIVISION_BY_ZERO Severe Service functioned correctly. The operation was not performed because the Denominator value is zero. 43.3.4.12 GCD, Modular Inverse 43.3.4.12.1 Purpose The purpose of this command is to compute the Greatest Common Divisor (GCD) and the Modular Inverse.
PAGE 1478
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • • • • • X (pointed by {nu1XBase,u2Length}) filled with X (with MSB word to zero) Y (pointed by {nu1YBase,u2Length}) filled with Y (with MSB word to zero) A (pointed by {nu1ABase,u2Length}) to contain calculated A Z (pointed by {nu1ZBase,u2Length}) to contain calculated Z The workspace (pointed by {nu1WorkSpace,32}) 43.3.4.12.4 Parameters Definition Table 43-37. GCD Service Parameters Parameter Type Dir.
PAGE 1479
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.4.12.
PAGE 1480
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Important: When using this service, be sure to strictly follow the directives given for the RNG on the chip you use (particularly initialization, seeding) and compulsorily start the RNG. If the directives require not to use this service, follow them and use the proposed method to get random numbers. This service only has the option to get random numbers and does not seed, initialize or start the RNG.
PAGE 1481
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) In the generation of a random number from the Deterministic RNG service, the following parameters need to be provided: • • • • XKey the input and output Key (pointed by {nu1XKeyBase,u2XKeyLength}) XSeed the input Seed (pointed by {nu1XseedBase,u2XKeyLength}) Q the prime number (pointed by {nu1QBase, 20bytes}) R the generated number area (pointed by {nu1RBase, 20bytes}) 43.3.4.13.
PAGE 1482
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter Type Direction Location Data Length Before After Executing the Executing the Service Service u2XKeyLength u2 I – – Length of XKey, Xseed[0] and Xseed[1] Length of XKey, Xseed[0] and Xseed[1] nu1QBase nu1 I Crypto RAM 20 bytes Base of Q Base of Q nu1RBase nu1 I Crypto RAM u2RLength Base of R Base of R filled with the result on 20 bytes Note: 1.
PAGE 1483
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) } else // Manage the error 43.3.4.13.9 Constraints Random Number Generation The following conditions must be avoided to ensure that the service works correctly: • {nu1RBase,u2RLength} not in RAM • {nu1RBase,u2RLength} not accessible or authorized for writing Deterministic Random Number Generation The length of the parameter nu1XSeedbase is: XSeedLength = max( 2*u2XKeyLength, 44 bytes) The max() macro takes a maximum of two values.
PAGE 1484
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • In GF(2n): The modulus is P[X] with length NLength in bytes For the exact calculus of NLength see below. Table 43-43. Modular Reduction Modes Modular Reduction Form Input Dynamic Result Dynamic Comments Fast GF(p): 0 ≤ Input < (N2) * (232) GF(p): 0 ≤ Res < N * 4 The fastest reduction available, needs a precomputed constant.
PAGE 1485
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • Operation is a Modular Reduction. • Operation is a Normalization. 43.3.5.1.2 How to Use the Service 43.3.5.1.3 Description This service performs one of the following operations: • • • • Setup of the Fast or Normalize functions: generation of the reduction constant Fast Modular Reduction Big Modular Reduction (using Euclide’s division) Normalization The service name for this operation is RedMod. 43.3.5.1.
PAGE 1486
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • • • • – The Normalize computation accept as entry a value whose length is lower or equal to u2ModLength + 4 (that is, for example, a value yet reduced but not normalized.). The u2ModLength + 4 MSB bytes are cleared at the beginning of the computation. – in case of Fast RedMod computations, the value X mayverify: X < (N2) *(232).
PAGE 1487
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.5.1.7 Modular Reductions Service Parameters Definition Table 43-44. RedMod Service Parameters Parameter Type Direction Location Data Length Before Executing the Service After Executing the Service u2Options u2 I – – Options (see below) Options (see below) Specific/CarryIn Bits I – – Must be set to zero.
PAGE 1488
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.5.1.8 Fast Modular Reductions Service Parameters Definition Table 43-45. Fast RedMode and Normalize Service Parameters Parameter Type Direction Location Data Length Before After Executing Executing the the Service Service u2Options u2 I – – Options (see below) Options (see below) Specific/CarryIn Bits I – – Must be set to zero.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1490
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) For this command three exclusive options can be specified. The following table lists the operations that can be performed. Table 43-47.
PAGE 1491
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) – CnsLength = u2ModLength +12 • For the Fast Reduction and Normalize: – RLength = u2ModLength +4 – CnsLength = u2ModLength +8 • For the BigRedMod: – RLength = u2ModLength +4 – CnsLength =64 The following combinations of input values should be avoided in the case of a modular reduction ‘alone’, meaning that it has not been requested as an option of any other command: • nu1ModBase, nu1CnsBase, nu1RBase, nu1XBase are not aligned on 32-bit
PAGE 1492
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.5.2.2 How to Use the Service 43.3.5.2.3 Description Important: Before using these functions, ensure that the constant Cns has been calculated with the Setup of the Modular Reductions service. This service processes the following operation: The service name for this operation is ExpMod.
PAGE 1493
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1494
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) There is no difference on the final result when using any of the options for this service. The choice has to be made according to the available resources (RAM, Time) and also taking into account the expected security level. For this service, two exclusive Calculus Modes are possible. The following table describes the Calculus Mode Options. Table 43-51.
PAGE 1495
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) // Depending on the option specified, not all fields should be filled PUKCL_ExpMod(nu1ModBase) = ; PUKCL_ExpMod(u2ModLength) = ; PUKCL_ExpMod(nu1CnsBase) = ; PUKCL_ExpMod(nu1XBase) = ; PUKCL_ExpMod(nu1PrecompBase) = ; PUKCL_ExpMod(pfu1ExpBase) = ; PUKCL_ExpMod(u2Ex
PAGE 1496
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1497
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Note: When using this service be sure to follow the directives given for the RNG on the chip you use (particularly initialization, seeding) and compulsorily start the RNG.
PAGE 1498
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter Typ e Direction Location Data Length Before Executing the Service After Executing the Service u2MaxIncrement u2 I – – Maximum Increment (see Note 4) Maximum Increment Note: 1. This zone contains the number to be either tested or used as a seed for generation. It has to be provided with one zero word on the MSB side. This area has supplementary constraints (see the following Important note).
PAGE 1499
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) PUKCL(u2Options) = PUKCL_EXPMOD_REGULARRSA | PUKCL_EXPMOD_WINDOWSIZE_2; The following table describes the PrimeGen service features available from the various options. Table 43-57. PrimeGen Service Options Option Method Used PUKCL_PRIMEGEN_TEST This option is used to specify that only tests will be made on the provided number.
PAGE 1500
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Option Specified Size of the PrecompBase Workspace (bytes) PUKCL_EXPMOD_WINDOWSIZE_4 max( 10*(u2NLength + 4) u2NLength + 72) + 8 Content of the Workspace x x3 x5 x7 x9 x11 x13 x15 The following table provides the maximum sizes for the Prime Generation depending on the window size. Table 43-60.
PAGE 1501
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • {nu1PrecompBase,} overlaps with either: {nu1NBase, u2NLength + 4}, {nu1CnsBase, u2NLength + 12} {nu1RndBase, u2NLength + 12} or {nu1ExpBase, u2ExpLength + 4} • {nu1RndBase,3*u2NLength + 24} overlaps with either: {nu1NBase, u2NLength + 4},{nu1CnsBase, u2NLength + 12} {nu1XBase, u2NLength + 12} or {nu1ExpBase, u2ExpLength + 4} • {nu1NBase, u2NLength + 4} overlaps {nu1CnsBase, u2NLength +12} 43.3.5.3.
PAGE 1502
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • Calculate the parameters from E: EP = E–1mod(P – 1) EQ = E–1mod(Q – 1) Rval = P–1mod(Q) In this computation, the following parameters need to be provided: • • • • • X the input number (pointed by {nu1XBase,2*u2ModLength +16}) P and Q the primes (pointed by {nu1ModBase,2*u2ModLength +8}).
PAGE 1503
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter Type Direction Location Data Length Before Executing the Service After Executing the Service u1Blinding (see Note 3) u4 – Exponent unblinding value Exponent unblinding value I – Note: 1. This zone contains the number to be exponentiated (u2ModLength bytes) and is used during the computations as a workspace (four 32-bit words longer than the number to be exponentiated).
PAGE 1504
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Option Explanation PUKCL_EXPMOD_REGULARRSA Performs a Regular computation, slower than the Fast version, but using regular calculus methods. For this service, four window sizes for the Modular Exponentiation Steps are possible. The window size in bits is those of the windowing method used for the exponent.
PAGE 1505
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Table 43-65. CRT Service Crypto RAM Option Exponent Area Option Purpose PUKCL_EXPMOD_EXPINPUKCCRAM The exponent area can be read from any data space of memory, including Crypto RAM. When at least one word the exponent is in Crypto RAM, this option has to be set. 43.3.5.4.6 Code Example PUKCL_PARAM PUKCLParam; PPUKCL_PARAM pvPUKCLParam = &PUKCLParam; PUKCL(u2Option) =...
PAGE 1506
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Figure 43-2. Modulus P and Q in {nu1ModBase, 2*u2ModLength + 8} Figure 43-3. Value X in {nu1XBase, 2*u2ModLength + 16} Figure 43-4. Exponents EP and EQ in {fnu1ExpBase, 2*u2ExpLength + 8} © 2019 Microchip Technology Inc.
PAGE 1507
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Figure 43-5. Value Rval and Precomp in {nu1PrecompBase, RandPrecompLen} 43.3.5.4.9 CRT Service Modular Exponentiation Maximum Size The following table details the maximum size in bits of P or Q, of N and of EP or EQ.
PAGE 1508
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Characteristics of the Operation P or Q Max Bit Sizes Exponent not in Crypto RAM, 4 bits window 2688 N Max Bit Sizes EP or EQ Max Bit Sizes 5376 43.3.5.4.10 Status Returned Values Table 43-67. CRT Service Return Codes 43.3.
PAGE 1509
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.1.2 Points Representations Depending on the representation (Projective or Affine), points are represented tn memory, as shown in the following figure. Figure 43-6. Points Representation in Memory In this figure, the modulus is represented as a reference, and to show that coordinates are always to be provided on the length of the modulus plus one 32-bit word. The different types of representations are as follows: Note: 1.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Note: Most of the Elliptic Curve computations are reduced modulo P. In many functions the reductions are made with the Fast Reduction.
PAGE 1511
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.2.4 Parameters Definition Table 43-68.
PAGE 1512
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • All overlapping between {nu1ModBase, u2ModLength + 4}, {nu1CnsBase, u2ModLength +8}, {nu1PointABase, 3*u2ModLength + 12}, {nu1PointBBase, 3*u2ModLength + 12} and {nu1Workspace, 5*u2ModLength + 32} 43.3.6.2.7 Status Returned Values Table 43-69. ZpEccAddFast Service Return Codes Returned Status Importance Meaning PUKCL_OK – The computation passed without problem. 43.3.6.3 Point Addition and Subtraction 43.3.6.3.
PAGE 1513
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1514
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • All overlapping between {nu1ModBase, u2ModLength + 4}, {nu1CnsBase, u2ModLength +8}, {nu1PointABase, 3*u2ModLength + 12}, {nu1PointBBase, 3*u2ModLength + 12} and {nu1Workspace, 5*u2ModLength + 32} 43.3.6.3.7 Status Returned Values Table 43-71. ZpEccAddFast Service Return Codes Returned Status Importance Meaning PUKCL_OK – The computation passed without problem. 43.3.6.4 Fast Point Doubling 43.3.6.4.
PAGE 1515
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1516
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.4.7 Status Returned Values Returned Status Importance Meaning PUKCL_OK – The computation passed without problem. 43.3.6.5 Fast Multiplying by a Scalar Number of a Point 43.3.6.5.1 Purpose This service is used to multiply a point by an integral constant K on a given elliptic curve over GF(p). 43.3.6.5.2 How to Use the Service 43.3.6.5.
PAGE 1517
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1518
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.5.7 Status Returned Values Returned Status Importance Meaning PUKCL_OK – The computation passed without problem. 43.3.6.6 Quick Dual Multiplying by Two Scalar Numbers and Two Points 43.3.6.6.1 Purpose This service is used to multiply two points by two integral constants K1 and K2, and then provide the addition of these multiplications results.
PAGE 1519
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Important: Please calculate precisely the length of areas with the formulas. Ensure that the pu1 type is a pointer on 4 bytes and contains the full address (see 43.3.3.4 Aligned Significant Length ). Table 43-74.
PAGE 1520
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • the indication of the presence of the scalars in system RAM Note: Please check precisely if one part of the scalars is in Crypto RAM. If this is the case, the PUKCL_ZPECCMUL_SCAL_IN_CLASSIC_RAM option must not be used. The u2Options number is calculated by an “Inclusive OR” of the options.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Table 43-76. ZpEccQuickDualMulFast Service System RAM Scalar Options Option Purpose PUKCL_ZPECCMUL_SCAL_IN_CLASSIC_RAM The scalars can be located in Crypto RAM or in system RAM. If both scalars are entirely in system RAM with no part in Crypto RAM this can be signaled by using this option . In all other cases this option must not be used. 43.3.6.6.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Figure 43-7. Modulus P and Cns{pu1ModCnsBase, 2*u2ModLength + 16} Figure 43-8. Points A and B {pu1PointABase, [(3*(u2ModLength + 4)) * (2(WA-2))] Or [(3*(u2ModLength + 4)) * (2(WB-2))]} © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Figure 43-9. Scalars KA and KB {pu1KABBase, 2 * u2KLength + 8} Figure 43-10. The a parameter and Workspace {pu1AWorkBase, 9*u2ModLength + 48} © 2019 Microchip Technology Inc.
PAGE 1524
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.6.9 Status Returned Values Returned Status Importance Meaning PUKCL_OK – The computation passed without problem. 43.3.6.7 Projective to Affine Coordinates Conversion 43.3.6.7.1 Purpose This service is used to perform a point coordinates conversion from projective representation to affine. 43.3.6.7.2 How to Use the Service 43.3.6.7.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter Type Direction Location Data Length Before After Executing Executing the the Service Service nu1PointABase nu1 I Crypto RAM 3*u2ModLength + 12 Input point A Resulting point A in affine coordinates nu1Workspace nu1 I Crypto RAM 4*u2ModLength + 48 – Workspace 43.3.6.7.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.8 Affine to Projective Coordinates Conversion 43.3.6.8.1 Purpose This service is used to perform a point coordinates conversion from an affine point representation to projective. 43.3.6.8.2 How to Use the Service 43.3.6.8.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) PUKCL (u2Option) = 0; PUKCL PUKCL PUKCL PUKCL PUKCL ...
PAGE 1528
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Important: Before using this service: • Ensure that the constant Cns has been calculated with the setup of the Modular Reduction service. • Be sure to follow the directives given for the RNG on the chip you use (particularly initialization, seeding) and compulsorily start the RNG . 43.3.6.9.4 Parameters Definition Table 43-81.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.9.6 Constraints No overlapping between either input and output are allowed.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) nu1ModBase nu1 I Crypto RAM u2ModLength + 4 Base of modulus P Base of modulus P nu1CnsBase nu1 I Crypto RAM u2ModLength + 8 Base of Cns Base of Cns u2ModLength u2 I – Length of modulus P Length of modulus P nu1PointBase nu1 I Crypto RAM 3*u2ModLength + 12 Input point unchanged nu1AParam nu1 I Crypto RAM u2ModLength + 4 The parameter a The parameter a nu1BParam nu1 I Crypto RAM u2ModLength + 4 The parame
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.10.7 Status Returned Values Table 43-84. ZpEcPointIsOnCurve Service Return Codes Returned Status Importance Meaning PUKCL_OK – The point is on the curve. PUKCL_POINT_IS_NOT_ON_ CURVE Warning The point is not on the curve. PUKCL_POINT_AT_INFINITY Warning The input point has its Z equal to zero, so it’s a representation of the infinite point. 43.3.6.11 Generating an ECDSA Signature (Compliant with FIPS 186-2) 43.3.6.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • Generally, u2ScalarLength is equal to (u2ModLength) or (u2ModLength + 4) Important: For the ECDSA signature generation be sure to follow the directives given for the RNG on the chip you use (particularly initialization, seeding) and compulsorily start the RNG. The scalar number k must be selected at random. This random must be generated before the call of the ECDSA signature.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.11.4 Parameters Definition Table 43-85.
PAGE 1534
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.11.
PAGE 1535
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.6.12 Verifying an ECDSA Signature (Compliant with FIPS186-2) 43.3.6.12.1 Purpose This service is used to verify an ECDSA signature following the FIPS 186-2. It performs the second step of the Signature Verification. A hash value (HashVal) must be provided as input, it has to be previously computed from the message to be signed using a secure hash algorithm. As second significant input, the Signature is provided to be checked.
PAGE 1536
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1537
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) PUKCL_ZpEcDsaVerify(nu1ScalarNumber) = ; PUKCL_ZpEcDsaVerify(nu1OrderPointBase) = ; PUKCL_ZpEcDsaVerify(nu1ABase) = ; PUKCL_ZpEcDsaVerify(nu1Workspace) = ; PUKCL_ZpEcDsaVerify(nu1HashBase) = ; PUKCL_ZpEcDsaVerify(u2ScalarLength) = < Length of ScalarNumber>; ...
PAGE 1538
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) This service checks the signature and fills the status accordingly. Important: This service has a quick implementation without additional security. 43.3.6.13.2 How to Use the Service 43.3.6.13.3 Description The operation performed is: Verify = EcDsaVerifySignature(PtA, HashVal, Signature, CurveParameters, PublicKey) The points used for this operation are represented in different coordinate systems.
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SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Table 43-89.
PAGE 1540
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • PointABase • PointPublicKeyGen • AWorkBase 43.3.6.13.5 Options The options are set by the u2Options input parameter, which is composed of: • the mandatory windows sizes WA (window for Point A) and WB (window for Point Public Key) • the indication of the presence of the Point Signature in system RAM Important: Please check precisely if the Point Signature is in Crypto RAM.
PAGE 1541
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) The following table details the size of the point and the precomputation table, depending on the chosen window size option. Table 43-91.
PAGE 1542
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • pu1ModCnsBase, pu1PointABase, pu1PointPublicKeyGen, pu1PointSignature,pu1OrderPointBase, pu1AWorkBase or pu1HashBase are not aligned on 32-bit boundaries • {pu1ModCnsBase, u2ModLength + 4 + u2MaxLength + 12}, {pu1PointABase, (3 * u2ModLength + 12)* (2(WA-2))}, {pu1PointPublicKeyGen, (3 * u2ModLength + 12) * (2(WPub-2))}, {pu1OrderPointBase, u2ScalarLength + 4}, {nu1ABase, u2ModLength + 4}, {pu1AWorkBase, (u2ModLength + 4) + (8 * u2Ma
PAGE 1543
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Figure 43-12. Points A {pu1PointABase, (3*(u2ModLength + 4)) * (2(WA-2))} and Public Key Gen {pu1PointPublicKeyGen, (3*(u2ModLength + 4)) * (2(WB-2))} Figure 43-13. PointSignature {pu1PointSignature, 2 * u2ScalarLength + 8} © 2019 Microchip Technology Inc.
PAGE 1544
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Figure 43-14. The a parameter and Workspace {pu1AWorkBase, 9*u2ModLength + 48} 43.3.7 Elliptic Curves Over GF(2n) Services This section provides a complete description of the currently available elliptic curve over Polynomials in GF(2n) services. These services process Polynomials in GF(2n) only.
PAGE 1545
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) In GF(2n) fully reduced polynomials are of degree strictly lower than degree(P[X]). In many cases the polynomials used in this library are only partially reduced and so have a degree higher or equal than degree(P[X]), but this degree is maintained strictly lower than (degree(P[X]) + 15). 43.3.7.1.
PAGE 1546
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) �Pr�� < � × �15 Projective representation: �� = �Pr�� < � × �15 �Pr�� < � × �15 Note: 1. The minimum value for u2ModLength is 12 bytes. Therefore, the significant length of the modulus must be at least three 32-bit words. 2. In some cases the point can be the infinite point. In this case it is represented with its Z coordinates equal or congruent to zero. 43.3.7.1.
PAGE 1547
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.7.2.2 How to Use the Service 43.3.7.2.3 Description The operation performed is: PtC = PtA + PtB In this computation, the following parameters need to be provided: • Point A the input point is filled in projective coordinates (X,Y,Z) (pointed by {nu1PointABase, 3*u2ModLength + 12}). This point can be the Infinite Point.
PAGE 1548
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter Type Direction Location Data Length Before Executing the Service After Executing the Service nu1ABBase nu1 I Crypto RAM u2ModLength + 4 Parameter a of the elliptic curve Unchanged nu1Workspace nu1 I Crypto RAM 7*u2ModLength + 40 – Corrupted workspace 43.3.7.2.
PAGE 1549
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.7.3.2 How to Use the Service 43.3.7.3.3 Description The operation performed is: PtC = 2 × PtA In this computation, the following parameters need to be provided: • A the input point is filled in projective coordinates (X,Y,Z) (pointed by {nu1PointABase, 3*u2ModLength + 12}). This point can be the Infinite Point.
PAGE 1550
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.7.3.5 Code Example PUKCL_PARAM PUKCLParam; PPUKCL_PARAM pvPUKCLParam = &PUKCLParam; PUKCL (u2Option) = 0; PUKCL PUKCL PUKCL PUKCL PUKCL PUKCL ...
PAGE 1551
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • • • • P the modulus filled (pointed by {nu1ModBase,u2ModLength + 4}) The workspace not initialized (pointed by {nu1WorkSpace, 8*u2ModLength + 44} The a and b parameters relative to the elliptic curve (pointed by {nu1ABBase,2*u2ModLength + 8}) K the scalar number (pointed by {nu1ScalarNumber,u2ScalarLength + 4}) The resulting C point is represented in projective coordinates (X,Y,Z) and is stored at the very same place than the input
PAGE 1552
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) PUKCL _GF2NEccMul(nu1ModBase) = ; PUKCL _GF2NEccMul(u2ModLength) = ; PUKCL _GF2NEccMul(nu1CnsBase) = ; PUKCL _GF2NEccMul(nu1PointBase) = ; PUKCL _GF2NEccMul(nu1ABase) = ; PUKCL _GF2NEccMul(nu1KBase) =
PAGE 1553
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • A the input point is filled in projective coordinates (X,Y,Z) or affine coordinates for X and Y, and setting Z to 1 (pointed by {nu1PointABase,3*u2ModLength + 12}). The Point A can be the point at infinity. In this case, the u2Status returned is PUKCL_POINT_AT_INFINITY.
PAGE 1554
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ... } else // Manage the error 43.3.7.5.6 Constraints No overlapping between either input and output are allowed.
PAGE 1555
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.7.6.4 Parameters Definition Table 43-102.
PAGE 1556
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.7.6.7 Status Returned Values Table 43-103. GF2NEcConvAffineToProjective Service Return Codes Returned Status Importance Meaning PUKCL_OK – The computation passed without problem. 43.3.7.7 Randomize Coordinate 43.3.7.7.1 Purpose This service is used to convert the Projective representation of a point to another Projective representation. 43.3.7.7.2 How to Use the Service 43.3.7.7.
PAGE 1557
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Parameter Type Direction Location nu1PointBase nu1 I Crypto RAM 3*u2ModLength + 12 Input point Resulting point nu1RandomBase nu1 I Crypto RAM u2ModLength + 4 Random Corrupted nu1Workspace I Crypto RAM 3*u2ModLength + 28 – Workspace nu1 Data Length Before After Executing the Executing the Service Service 43.3.7.7.
PAGE 1558
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.7.7.7 Status Returned Values Table 43-105. GF2NEcRandomiseCoordinate Service Return Codes Returned Status Importance Meaning PUKCL_OK – The computation passed without problem. 43.3.7.8 Point is on Elliptic Curve 43.3.7.8.1 Purpose This service is used to test whether the point is on the curve. 43.3.7.8.2 How to Use the Service 43.3.7.8.
PAGE 1559
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) 43.3.7.8.
PAGE 1560
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) A scalar number must be provided, as described in the FIPS 186-2. The result (R,S) is computed by this service. If S equals zero, the status is set to PUKCL_WRONG_SELECT_NUMBER. 43.3.7.9.2 How to Use the Service 43.3.7.9.
PAGE 1561
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) • Compute a S value using R, the scalar number, the private key and the provided hash value. Note that the resulting signature (R,S) is stored at the place of the input A point. • If all is correct and S is different from zero, the status is set to PUKCL_OK. If all is correct and S equals zero,the status is set to PUKCL_WRONG_SELECT_NUMBER.
PAGE 1562
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1563
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) PUKCL _GF2NEcDsaGenerate(nu1ScalarNumber) = ; PUKCL _GF2NEcDsaGenerate(nu1OrderPointBase) = ; PUKCL _GF2NEcDsaGenerate(nu1ABase) = ; PUKCL _GF2NEcDsaGenerate(nu1Workspace) = ; PUKCL _GF2NEcDsaGenerate(nu1HashBase) = ; ...
PAGE 1564
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) Verify = EcDsaVerifySignature(PtA, HashVal, Signature, CurveParameters, PublicKey) The points used for this operation are represented in different coordinate systems.
PAGE 1565
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1566
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) else } if(PUKCL(u2Status) == PUKCL_WRONG_SIGNATURE) { ... } else // Manage the error 43.3.7.10.6 Constraints No overlapping between either input and output are allowed.
PAGE 1567
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1568
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued PUKCL Service STACK Usage (Bytes) ZpEcRandomiseCoordinate 56 GF2NEccAddFast 128 GF2NEcConvProjToAffine 264 GF2NEcConvAffineToProjective 56 GF2NEccDblFast 136 GF2NEccMulFast 208 GF2NEcDsaGenerateFast 376 GF2NEcDsaVerifyFast 440 GF2NEcRandomiseCoordinate 56 43.3.8.2 Parameter Size Limits for Different Services The following table lists parameter size limits for different services.
PAGE 1569
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........
PAGE 1570
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued API Min/Max Sizes Comments ECDSA Verify GF(2n) Modulus: 12 to 180 bytes Supposing Length(Scalar) = Length(Modulus) (up to 571 bits for common curves) ECDSA Quick Verify GF(2n) Modulus: 12 to 140 bytes (up to 571 bits for common curves) Supposing Length(Scalar) = Length(Modulus) 43.3.8.3 Service Timing The values in the following tables are estimated performances for CPU clock of 120 MHz.
PAGE 1571
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Operation Clock Cycles Timing One block RSA 2048 encryption / signature verification. 0.24 MCycles 2 ms No CRT, Fast implementation, W=1 Exponent=3 RSA 2048 encryption / signature verification. 0.24 MCycles 2 ms No CRT, Fast implementation, W=1 Exponent=0x10001 Table 43-116. RSA4096 Operation Clock Cycles Timing One block RSA 4096 Decryption / signature generation.
PAGE 1572
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Operation Clock Cycles Timing One Block Regular Generation of two primes, Prime_Length=2048 bits, W=4, Rabin Miller Iterations Number = 3, (Standard Deviation for 200 samples) Std Dev = 3,05 GCycles Std Dev = 25.4s 43.3.8.3.
PAGE 1573
SAM D5x/E5x Family Data Sheet Public Key Cryptography Controller (PUKCC) ...........continued Operation CPU Cycles Timing One block ECDSA GF(2n) B409 Verify 13.8 Mcycles 115 ms ECDSA GF(2n) B571 Generate Fast 15.1 Mcycles 125 ms ECDSA GF(2n) B571 Verify 30.1 MCycles 251 ms © 2019 Microchip Technology Inc.
PAGE 1574
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44. TRNG – True Random Number Generator 44.1 Overview The True Random Number Generator (TRNG) generates unpredictable random numbers that are not generated by an algorithm. It passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3. 44.
PAGE 1575
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator The TRNG interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Related Links 18. PM – Power Manager 44.6.5 Sleep Mode Operation 44.5.3 Clocks The TRNG bus clock (CLK_TRNG_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_TRNG_APB can be found in Peripheral Clock Masking. Related Links 15.
PAGE 1576
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.6 Functional Description 44.6.1 Principle of Operation When the TRNG is enabled, the peripheral starts providing new 32-bit random numbers every 84 CLK_TRNG_APB clock cycles. The TRNG can be configured to generate an interrupt or event when a new random number is available. Figure 44-2. TRNG Data Generation Sequence Clock ENABLE 84 clock cycles 84 clock cycles 84 clock cycles Interrupt Read TRNG_ISR Read DATA 44.6.
PAGE 1577
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, or the interrupt is disabled. See 44.8.5 INTFLAG for details on how to clear interrupt flags. Note that interrupts must be globally enabled for interrupt requests to be generated. Related Links 10.2 Nested Vector Interrupt Controller 44.6.
PAGE 1578
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 RUNSTDBY ENABLE 0x01 ... Reserved 0x03 0x04 EVCTRL 7:0 DATARDYEO 0x05 ... Reserved 0x07 0x08 INTENCLR 7:0 DATARDY 0x09 INTENSET 7:0 DATARDY 0x0A INTFLAG 7:0 DATARDY 0x0B ... Reserved 0x1F 0x20 44.8 DATA 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] Register Description Registers can be 8, 16, or 32 bits wide.
PAGE 1579
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.8.1 Control A Name: Offset: Reset: Property: Bit Access Reset 7 CTRLA 0x00 0x00 PAC Write-Protection 6 5 4 3 2 1 RUNSTDBY ENABLE R/W R/W 0 0 0 Bit 6 – RUNSTDBY Run in Standby This bit controls how the ADC behaves during standby sleep mode: Value Description 0 The TRNG is halted during standby sleep mode. 1 The TRNG is not stopped in standby sleep mode. Bit 1 – ENABLE Enable Value Description 0 The TRNG is disabled.
PAGE 1580
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.8.2 Event Control Name: Offset: Reset: Property: Bit 7 EVCTRL 0x04 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 2 1 0 DATARDYEO Access R/W Reset 0 Bit 0 – DATARDYEO Data Ready Event Output This bit indicates whether the Data Ready event output is enabled and whether an output event will be generated when a new random value is ready.
PAGE 1581
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.8.3 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x08 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
PAGE 1582
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.8.4 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x09 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 1583
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.8.5 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x0A 0x00 - 6 5 4 3 2 1 0 DATARDY Access R/W Reset 0 Bit 0 – DATARDY Data Ready This flag is set when a new random value is generated, and an interrupt will be generated if INTENCLR/ SET.DATARDY=1. This flag is cleared by writing a '1' to the flag or by reading the DATA register. Writing a '0' to this bit has no effect.
PAGE 1584
SAM D5x/E5x Family Data Sheet TRNG – True Random Number Generator 44.8.
PAGE 1585
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45. ADC – Analog-to-Digital Converter 45.1 Overview The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has up to 12bit resolution, and is capable of a sampling rate of up to 1MSPS. The input selection is flexible, and both differential and single-ended measurements can be performed. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
PAGE 1586
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter • • • • • • • Built-in internal reference and external reference options Event-triggered conversion for accurate timing (one event input) Optional DMA transfer of conversion settings or result Hardware gain and offset compensation Averaging and oversampling with decimation to support up to 16-bit result Selectable sampling time Flexible Power / Throughput rate management ADC0 can be configured to serve the Peripheral Touch Controller (PTC).
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SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Note: One signal can be mapped on several pins. Related Links 6. I/O Multiplexing and Considerations 45.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 45.5.1 I/O Lines Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT). Related Links 32. PORT - I/O Pin Controller 45.5.
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SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.5.6 Events The events are connected to the Event System. Related Links 31. EVSYS – Event System 45.5.7 Debug Operation When the CPU is halted in debug mode the ADC will halt normal operation. The ADC can be forced to continue operation during debugging. Refer to DBGCTRL register for details. Related Links 45.8.3 DBGCTRL 45.5.
PAGE 1589
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter • Control A (CTRLA), except ENABLE and SWRST bits • Event Control register (EVCTRL) • Calibration register (CALIB) Enable-protection is denoted by the "Enable-Protected" property in the register description. 45.6.2.2 Enabling, Disabling, and Resetting The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled by writing CTRLA.ENABLE=0.
PAGE 1590
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Figure 45-2. ADC Prescaler DIV256 DIV128 DIV64 DIV32 DIV16 DIV8 DIV4 9-BIT PRESCALER DIV2 GCLK_ADCx CTRLA.PRESCALER[2:0] CLK_ADCx Note: The minimum prescaling factor is DIV2. 45.6.2.5 Reference Configuration The ADC has various sources for its reference voltage VREF. The Reference Voltage Selection bit field in the Reference Control register (REFCTRL.REFSEL) determines which reference is selected.
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SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Figure 45-3. ADC Timing for One Conversion in 12-bit Resolution CLK_ADC START STATE SAMPLING MSB 9 10 8 7 6 5 4 3 2 1 LSB INT The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion with sampling time increased to six CLK_ADC cycles. Figure 45-4.
PAGE 1592
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Figure 45-7. ADC Timing for Free Running in 8-bit Resolution CLK_ADC CONVERT STATE LSB SAMPLING MSB 6 5 4 3 2 1 LSB SAMPLING MSB 6 5 4 3 2 1 LSB SAMPLING MSB INT The propagation delay of an ADC measurement is given by: PropagationDelay = 1 + Resolution �ADC Example. In order to obtain 1MSPS in 12-bit resolution with a sampling time length of four CLK_ADC cycles, fCLK_ADC must be 1MSPS * (4 + 12) = 16MHz.
PAGE 1593
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Table 45-2. Accumulation Number of Accumulated Samples AVGCTRL.
PAGE 1594
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter ...........continued Number of AVGCTRL. Accumulated SAMPLENUM Samples Intermediate Result Precision Number of Automatic Right Shifts Division Factor AVGCTRL.
PAGE 1595
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter example in 8-bit mode, only the eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the sign bit, even if the ninth bit is zero. The INTFLAG.WINMON interrupt flag is set when either the conversion result matches the window monitor condition, when the Window Comparator Counter is not zero in case of accumulation with CTRLB.WINSS=1. 45.6.2.
PAGE 1596
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Sensor Channel Selection bit in the Voltage Reference System Control register (SUPC.VREF.TSSEL). SUPC ADC TSENSP TSENSP TSENSC ... TSENSC VREF.OE, VREF.TSEN, VREF.TSSEL ADC RESULT TP, TC INPUTCTRL.MUXPOS The state of the MUX input selection bit fields in the ADC Input Control register (ADC.INPUTCTRL.MUXPOS and MUXNEG) does not affect the sensor selection. • If the SUPC is in on-demand mode in (SUPC.VREF.ONDEMAND=1) and SUPC.VREF.
PAGE 1597
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter When one of these registers is written, the data is stored in the corresponding buffer as long as the current conversion is not impacted, and the corresponding busy status will be set in the Synchronization Busy register (SYNCBUSY). When a new RESULT is available, data stored in the buffer registers will be transfered to the ADC and a new conversion can start. 45.6.3.3 DMA Sequencing The ADC can sequence a series of conversion.
PAGE 1598
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter • The DMA Sequencing Stop bit in Input Control register is '1' (INPUTCTRL.DSEQSTOP = 1) and the ongoing DMA sequence is complete. One additional measurement will be done before the ADC is disabled. When the DMA sequencing is disable, the BUSY status bit in the DMA Sequential Status register (DSEQSTAT.BUSY) is cleared and the DMA trigger generation is disabled.
PAGE 1599
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Table 45-5. DSEQ Trigger Generation and Internal ADC Register updates Condition Value Action when DMA writes to DSEQDATA DSEQSTAT.INPUTCT RL or DSEQSTAT.CTRLB 0 • No DMA trigger is generated • No data in the memory must be reserved 1 • A DMA trigger is generated • One word (32-bit) must be reserved in the memory • INPUTCTRL ← DSEQDATA[15:0] if DSEQSTAT.INPUTCTRL = 1 • CTRLB ← DSEQDATA[31:16] if DSEQSTAT.CTRLB = 1 DSEQSTAT.
PAGE 1600
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter DMA Descriptor Setup and Data Memory Organization When DMA sequencing is enabled, the DMA Controller (DMAC) must be configured in the following way: • Select 32-bit beat size transfer (DMAC.BTCTRL.BEATSIZE=WORD). • Enable the source address increment options (DMAC.BTCTRL.SRCINC = 1, DMAC.BTCTRL.STEPSEL = SRC, DMAC.BTCTRL.STEPSIZE = X1). • Disable the destination address increment (DMAC.BTCTRL.DSTINC=0).
PAGE 1601
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter By default, a new conversion starts when a new start software or event trigger is received. It is also possible to automatically enable an ADC conversion by writing '1' to the AUTOSTART bit in DSEQCTRL register (DSEQCTRL.AUTOSTART). When set, the ADC automatically starts a new conversion when a DMA sequence is complete.
PAGE 1602
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter ADC0.DSEQCTRL ADC0.AVGCTRL ADC0.WINLT ADC0.SAMPCTRL ADC0.WINUT ADC0.EVCTRL ADC0.OFFSETCORR ADC0.SWTRIG ADC0.GAINCORR ADC0 ... ADCn INT.SIG ADC 0 ADC0.INPUTCTRL POST PROCESSING ADC0.RESULT ADC0.DSEQSTAT ADC0 ... ADCn ADC0.CTRLA INT1V INTVCC0 INTVCC1 VREFA ... VREFn PRESCALER ADC0.REFCTRL ADC0 ... ADCn INT.SIG ADC 1 ADC1.INPUTCTRL ADC1.RESULT POST PROCESSING ADC1.DSEQSTAT ADC0 ... ADCn INT1V INTVCC0 INTVCC1 VREFA ...
PAGE 1603
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter • Reset and reconfigure master ADC (ADC0.CTRLA.SWRST = 1) • Enable the flush event (EVCTRL.FLUSHEI = 1) Start Trigger (Software or Event) ADC0 Start Conversion 45.6.
PAGE 1604
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter The ADC can take the following actions on an input event: • Start conversion (START): Start a conversion. Refer to SWTRIG register for details. • Conversion flush (FLUSH): Flush the conversion. Refer to SWTRIG register for details. Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding action on input event. Clearing this bit disables the corresponding action on input event.
PAGE 1605
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter The following registers are synchronized when written: • • • • • • • • • • Input Control register (INPUTCTRL) Control B register (CTRLB) Reference Control (REFCTRL) Average control register (AVGCTRL) Sampling time control register (SAMPCTRL) Window Monitor Lower Threshold register (WINLT) Window Monitor Upper Threshold register (WINUT) Gain correction register (GAINCORR) Offset Correction register (OFFSETCORR) Software Trigger register (SWTRIG
PAGE 1606
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.7 Register Summary Offset Name 0x00 CTRLA 0x02 EVCTRL 7:0 0x03 DBGCTRL 7:0 0x04 INPUTCTRL 0x06 CTRLB 0x08 REFCTRL Bit Pos.
PAGE 1607
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter ...........continued Offset Name Bit Pos. 7:0 0x3C DSEQSTAT GAINCORR WINUT WINLT SAMPCTRL AVGCTRL REFCTRL CTRLB INPUTCTRL OFFSETCOR 15:8 R 23:16 31:24 0x40 RESULT BUSY 7:0 RESULT[7:0] 15:8 RESULT[15:8] 7:0 RESS[7:0] 15:8 RESS[15:8] 0x42 ... Reserved 0x43 0x44 RESS 0x46 ... Reserved 0x47 0x48 45.
PAGE 1608
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1609
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Value 0 1 Description The ADC is always on , if enabled. The ADC is enabled, when a peripheral is requesting the ADC conversion. The ADC is disabled if no peripheral is requesting it. Bit 6 – RUNSTDBY Run in Standby This bit controls how the ADC behaves during standby sleep mode. This bit is not synchronized. Note: For the slave ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
PAGE 1610
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Writing a '1' to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be disabled. Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
PAGE 1611
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.2 Event Control Name: Offset: Reset: Property: Bit 7 EVCTRL 0x02 0x00 PAC Write-Protection 6 Access Reset 5 4 3 2 1 0 WINMONEO RESRDYEO STARTINV FLUSHINV STARTEI FLUSHEI R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 5 – WINMONEO Window Monitor Event Out This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated when the window monitor detects something.
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SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Value 1 Description A flush and new conversion will be triggered on any incoming event. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.3 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x03 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. This bit should be written only while a conversion is not ongoing.
PAGE 1614
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1615
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Control register must be written with a corresponding value, as shown in “Table 54-24. Operating Conditions”.
PAGE 1616
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1617
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Bit 1 – FREERUN Free Running Mode Value Description 0 The ADC run in single conversion mode 1 The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes Bit 0 – LEFTADJ Left-Adjusted Result The high byte of the 12-bit result will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust the value in the RESULT register.
PAGE 1618
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.6 Reference Control Name: Offset: Reset: Property: Bit 7 REFCTRL 0x08 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 2 1 0 R/W R/W R/W 0 0 R/W R/W 0 0 0 REFCOMP Access Reset REFSEL[3:0] Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable The gain error can be reduced by enabling the reference buffer offset compensation. This will increase the start-up time of the reference.
PAGE 1619
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.7 Average Control Name: Offset: Reset: Property: Bit 7 AVGCTRL 0x0A 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 2 ADJRES[2:0] Access Reset 1 0 SAMPLENUM[3:0] R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 6:4 – ADJRES[2:0] Adjusting Result / Division Coefficient These bits define the division coefficient in 2^n steps.
PAGE 1620
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.8 Sampling Time Control Name: Offset: Reset: Property: Bit 7 SAMPCTRL 0x0B 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W 0 0 0 0 OFFCOMP Access Reset SAMPLEN[5:0] Bit 7 – OFFCOMP Comparator Offset Compensation Enable Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to temperature or voltage drift.
PAGE 1621
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1622
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1623
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.11 Gain Correction Name: Offset: Reset: Property: Bit 15 GAINCORR 0x10 0x0000 PAC Write-Protection, Write-Synchronized 14 13 12 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 GAINCORR[11:8] Access Reset Bit 7 6 5 4 GAINCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 11:0 – GAINCORR[11:0] Gain Correction Value If CTRLB.
PAGE 1624
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.12 Offset Correction Name: Offset: Reset: Property: Bit 15 OFFSETCORR 0x12 0x0000 PAC Write-Protection, Write-Synchronized 14 13 12 11 10 9 8 OFFSETCORR[11:8] Access Reset Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 OFFSETCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 11:0 – OFFSETCORR[11:0] Offset Correction Value If CTRLB.
PAGE 1625
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.13 Software Trigger Name: Offset: Reset: Property: Bit 7 SWTRIG 0x14 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 2 1 0 START FLUSH Access W RW Reset 0 0 Bit 1 – START Start ADC Conversion Writing a '1' to this bit will start a conversion or sequence. The bit is cleared by hardware when the conversion has started. Writing a '1' to this bit when it is already set has no effect.
PAGE 1626
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.14 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x2C 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
PAGE 1627
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.15 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x2D 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 1628
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.16 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x2E 0x00 – 6 5 4 3 Access Reset 2 1 0 WINMON OVERRUN RESRDY R/W R/W R/W 0 0 0 Bit 2 – WINMON Window Monitor Interrupt Flag This flag is cleared by writing a '1' to the flag or by reading the RESULT register.
PAGE 1629
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.17 STATUS Name: Offset: Reset: Property: STATUS 0x2F 0x00 - Bit 7 6 5 4 3 2 Access R R R R R R Reset 0 0 R 0 0 0 0 0 WCC[5:0] 1 0 ADCBUSY Bits 7:2 – WCC[5:0] Window Comparator Counter These bits indicates the number of sample matching with the window comparator. Writing a zero to this bit will have no effect. Writing a one to this bit will have no effect.
PAGE 1630
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1631
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Bit 7 – WINLT Window Monitor Lower Threshold Synchronization Busy This bit is cleared when the synchronization of WINLT register between the clock domains is complete. This bit is set when the synchronization of WINLT register between clock domains is started. Bit 6 – SAMPCTRL Sampling Time Control Synchronization Busy This bit is cleared when the synchronization of SAMPCTRL register between the clock domains is complete.
PAGE 1632
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1633
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1634
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Bit 5 – WINLT Window Monitor Lower Threshold Value Description 0 DMA update of the Window Monitor Lower Threshold register is disabled. 1 DMA update of the Window Monitor Lower Threshold register is enabled. Bit 4 – SAMPCTRL Sampling Time Control Value Description 0 DMA update of the Sampling Time Control register is disabled. 1 DMA update of the Sampling Time Control register is enabled.
PAGE 1635
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1636
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter Value 1 Description DMA update of the Window Monitor Lower Threshold register is enabled. Bit 4 – SAMPCTRL Sampling Time Control Value Description 0 DMA update of the Sampling Time Control register is complete or disabled. 1 DMA update of the Sampling Time Control register is enabled. Bit 3 – AVGCTRL Average Control Value Description 0 DMA update of the Average Control register is complete or disabled.
PAGE 1637
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.22 Result Name: Offset: Reset: Property: RESULT 0x40 0x0000 - Bit 15 14 13 12 Access R R R R Reset 0 0 0 0 Bit 7 6 5 4 11 10 9 8 R R R R 0 0 0 0 3 2 1 0 RESULT[15:8] RESULT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RESULT[15:0] Result Conversion Value These bits will hold up to a 16-bit ADC conversion result, depending on the configuration.
PAGE 1638
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.23 RESS Name: Offset: Reset: Property: RESS 0x44 0x0000 - Bit 15 14 13 12 11 10 9 8 Access R R R R Reset 0 0 R R R R 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RESS[15:8] RESS[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RESS[15:0] Last ADC Conversion Result These bits will hold up the last ADC conversion result. © 2019 Microchip Technology Inc.
PAGE 1639
SAM D5x/E5x Family Data Sheet ADC – Analog-to-Digital Converter 45.8.
PAGE 1640
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46. 46.1 AC – Analog Comparators Overview The Analog Comparator (AC) supports two individual comparators. Each comparator (COMP) compares the voltage levels on two inputs, and provides a digital output based on this comparison. Each comparator may be configured to generate interrupt requests and/or peripheral events upon several different combinations of input change. Hysteresis can be adjusted to achieve the optimal operation for each application.
PAGE 1641
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.3 Block Diagram Figure 46-1. Analog Comparator Block Diagram AIN0 + CMP0 COMP0 AIN1 - VDD SCALER HYSTERESIS ENABLE DAC INTERRUPTS INTERRUPT MODE COMPCTRLn WINCTRL ENABLE BANDGAP 46.4 GCLK_AC CMP1 COMP1 AIN3 EVENTS HYSTERESIS + AIN2 INTERRUPT SENSITIVITY CONTROL & WINDOW FUNCTION - Signal Description Signal Description Type AIN[3..0] Analog input Comparator inputs CMP[1..
PAGE 1642
SAM D5x/E5x Family Data Sheet AC – Analog Comparators Table 46-1. I/O Lines Instance Signal I/O Line Peripheral Function AC0 AIN0 PAxx A AC0 AIN1 PAxx A AC0 AIN2 PAxx A AC0 AIN3 PAxx A AC0 CMP0 PAxx A AC0 CMP1 PAxx A Related Links 32. PORT - I/O Pin Controller 46.5.2 Power Management The AC will continue to operate in any Sleep mode where the selected source clock is running. The AC’s interrupts can be used to wake up the device from Sleep modes.
PAGE 1643
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.5.7 Debug Operation When the CPU is halted in debug mode, the AC will halt normal operation after any on-going comparison is completed. The AC can be forced to continue normal operation during debugging. Refer to DBGCTRL for details. If the AC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 46.5.
PAGE 1644
SAM D5x/E5x Family Data Sheet AC – Analog Comparators • Event Control register (EVCTRL) Enable-protection is denoted by the "Enable-Protected" property in each individual register description. 46.6.2.2 Enabling, Disabling and Resetting The AC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The AC is disabled writing a '0' to CTRLA.ENABLE. The AC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST).
PAGE 1645
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.6.2.4.1 Continuous Measurement Continuous measurement is selected by writing COMPCTRLx.SINGLE to zero. In continuous mode, the comparator is continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always available in the Current State bit in the Status A register (STATUSA.STATEx). After the start-up time has passed, a comparison is done and STATUSA is updated.
PAGE 1646
SAM D5x/E5x Family Data Sheet AC – Analog Comparators Figure 46-3. Single-Shot Example GCLK_AC Write ‘1’ CTRLB.STARTx Write ‘1’ 2-3 cycles STATUSB.READYx 2-3 cycles tSTARTUP tSTARTUP Sampled Comparator Output For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs, the Power Manager will start GCLK_AC.
PAGE 1647
SAM D5x/E5x Family Data Sheet AC – Analog Comparators When the comparators are configured for Window mode and Single-shot mode, measurements are performed simultaneously on both comparators. Writing '1' to either Start Comparison bit in the Control B register (CTRLB.STARTx) will start a measurement. Likewise either peripheral event can start a measurement. Figure 46-4.
PAGE 1648
SAM D5x/E5x Family Data Sheet AC – Analog Comparators Figure 46-5. VDD Scaler COMPCTRLx.MUXNEG == 5 OR COMPCTRLx.MUXPOS == 4 SCALERx. VALUE 6 to COMPx 46.6.6 Input Hysteresis Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will help prevent constant toggling of the output, which can be caused by noise when the input signals are close to each other.
PAGE 1649
SAM D5x/E5x Family Data Sheet AC – Analog Comparators Figure 46-7. Single-Shot Filtering Sampling Clock Start tSTARTUP 3-bit Sampled Comparator Output 3-bit Majority Filter Output 5-bit Sampled Comparator Output 5-bit Majority Filter Output During Sleep modes, filtering is supported only for single-shot measurements. Filtering must be disabled if continuous measurements will be done during Sleep modes, or the resulting interrupt/event may be generated incorrectly. 46.6.
PAGE 1650
SAM D5x/E5x Family Data Sheet AC – Analog Comparators Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSEL[1:0]). Each interrupt source has an interrupt flag associated with it.
PAGE 1651
SAM D5x/E5x Family Data Sheet AC – Analog Comparators When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. The AC can also be used during sleep modes where the clock used by the AC is disabled, provided that the AC is still powered (not in shutdown). In this case, the behavior is slightly different and depends on the measurement mode, as listed in Table 46-2. Table 46-2. Sleep Mode Operation COMPCTRLx.
PAGE 1652
SAM D5x/E5x Family Data Sheet AC – Analog Comparators • Enable bit in Control register (CTRLA.ENABLE) • Enable bit in Comparator Control register (COMPCTRLn.ENABLE) The following registers are synchronized when written: • Window Control register (WINCTRL) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links 13.3 Register Synchronization © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.7 Register Summary Offset Name Bit Pos.
PAGE 1654
SAM D5x/E5x Family Data Sheet AC – Analog Comparators Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
PAGE 1655
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 Access Reset 2 1 0 ENABLE SWRST R/W W 0 0 Bit 1 – ENABLE Enable Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the corresponding bit in the Synchronization Busy register (SYNCBUSY.
PAGE 1656
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.2 Control B Name: Offset: Reset: Property: Bit 7 CTRLB 0x01 0x00 - 6 5 4 3 Access Reset 2 1 0 START1 START0 R/W R/W 0 0 Bits 0, 1 – STARTx Comparator x Start Comparison Writing a '0' to this field has no effect. Writing a '1' to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the Comparator x Control Register are '1' (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE).
PAGE 1657
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.3 Event Control Name: Offset: Reset: Property: Bit 15 EVCTRL 0x02 0x0000 PAC Write-Protection, Enable-Protected 14 Access Reset Bit 7 6 Access Reset 13 12 INVEI1 R/W 0 5 9 8 INVEI0 COMPEI1 COMPEI0 R/W R/W R/W 0 0 0 4 11 3 10 1 0 WINEO0 2 COMPEO1 COMPEO0 R/W R/W R/W 0 0 0 Bits 12, 13 – INVEIx Inverted Event Input Enable x Value Description 0 Incoming event is not inverted for comparator x.
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x04 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 1659
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x05 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x06 0x00 – 6 Access Reset 5 4 3 2 1 0 WIN0 COMP1 COMP0 R/W R/W R/W 0 0 0 Bit 4 – WIN0 Window 0 This flag is set according to the Window 0 Interrupt Selection bit group in the WINCTRL register (WINCTRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one. Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.7 Status A Name: Offset: Reset: Property: Bit 7 STATUSA 0x07 0x00 - 6 5 4 3 WSTATE0[1:0] 2 1 0 STATE1 STATE0 Access R R R R Reset 0 0 0 0 Bits 5:4 – WSTATE0[1:0] Window 0 Current State These bits show the current state of the signal if the window 0 mode is enabled. These values may change in during startup and measurement cycles. When polling for sample completion use the STATUSB.READY bit to signal completion.
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.8 Status B Name: Offset: Reset: Property: Bit 7 STATUSB 0x08 0x00 - 6 5 4 3 2 1 0 READY1 READY0 Access R R Reset 0 0 Bits 0, 1 – READYx Comparator x Ready This bit is cleared when the comparator x output is not ready. This bit is set when the comparator x output is ready. © 2019 Microchip Technology Inc.
PAGE 1663
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.9 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x09 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bits controls the functionality when the CPU is halted by an external debugger. Value Description 0 The AC is halted when the CPU is halted by an external debugger. Any on-going comparison will complete.
PAGE 1664
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.10 Window Control Name: Offset: Reset: Property: Bit 7 WINCTRL 0x0A 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 2 1 WINTSEL0[1:0] Access Reset 0 WEN0 R/W R/W R/W 0 0 0 Bits 2:1 – WINTSEL0[1:0] Window 0 Interrupt Selection These bits configure the interrupt mode for the comparator window 0 mode.
PAGE 1665
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.11 Scaler n Name: Offset: Reset: Property: Bit 7 SCALER 0x0C + n*0x01 [n=0..1] 0x00 PAC Write-Protection 6 5 4 3 2 1 0 R/W R/W R/W 0 0 R/W R/W R/W 0 0 0 0 VALUE[5:0] Access Reset Bits 5:0 – VALUE[5:0] Scaler Value These bits define the scaling factor for channel n of the VDD voltage scaler. The output voltage, VSCALE, is: �DD ⋅ VALUE+1 �SCALE = 64 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.12 Comparator Control n Name: Offset: Reset: Property: Bit 31 COMPCTRL 0x10 + n*0x04 [n=0..
PAGE 1667
SAM D5x/E5x Family Data Sheet AC – Analog Comparators Bits 21:20 – HYST[1:0] Hysteresis Level These bits indicate the hysteresis level of comparator n when hysteresis is enabled (COMPCTRLn.HYSTEN=1). Hysteresis is available only for continuous mode (COMPCTRLn.SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized.
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero. These bits are not synchronized.
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SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.
PAGE 1670
SAM D5x/E5x Family Data Sheet AC – Analog Comparators 46.8.14 Calibration Register Name: Offset: Reset: Property: Bit CALIB 0x24 0x0101 Enable-Protect, PAC Write-Protection 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit BIAS0[1:0] Access Reset R/W R/W 0 1 Bits 1:0 – BIAS0[1:0] COMP0/1 Bias Scaling This value from production test must be loaded from the NVM software calibration row into the CALIB register by software to achieve the specified accuracy.
PAGE 1671
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47. DAC – Digital-to-Analog Converter 47.1 Overview The Digital-to-Analog Converter (DAC) converts a digital value to a voltage. The DAC Controller controls two DACs, which can operate either as two independent DACs or as a single DAC in differential mode. Each DAC is 12-bit resolution and is capable of converting up to 1,000,000 samples per second (MSPS). 47.2 Features • • • • • • • • • 47.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter ...........continued Signal Description Type VREFA External reference Analog input One signal can be mapped on several pins. Important: When an analog peripheral is enabled, the analog output of the peripheral will interfere with the alternative functions of the output pads. This is also true even when the peripheral is used for internal purposes. Analog inputs do not interfere with alternative pad functions. Related Links 6.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter This generic clock is asynchronous to the bus clock (CLK_DAC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 47.6.8 Synchronization for further details. Related Links 15.6.2.6 Peripheral Clock Masking 14. GCLK - Generic Clock Controller 47.5.4 DMA The DMA request line is connected to the DMA Controller (DMAC).
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.5.9 Analog Connections The DAC has up to two analog output pins (VOUT0, VOUT1) and one analog input pin (VREFA) that must be configured first. When an internal input is used, it must be enabled before DAC Controller is enabled. The analog signals of AC, ADC, DAC and OPAMP can be interconnected. See Analog Connections of Peripherals for details. 47.6 Functional Description 47.6.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter • Select the refresh period with the Refresh Period bit field in DACCCTRLx.REFRESH[3:0]. Writing any value greater than '1' to the REFRESH bit field will enable and select the refresh mode. Refer to 47.6.9.3 Conversion Refresh for details. • Select the output buffer current according to data rate (for low power application) with the Current Control bit field DACCTRLx.CCTRL[1:0]. Refer to 47.6.9.2 Output Buffer Current Control for details.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Figure 47-2. Single DAC Conversion t0 t12 t24 GCLK_DAC 0x3FF DATAx 0xFFF Start of Conversion STATUS.EOCx 0xFFF VREF 0x7FF VREF/2 0x000 0 VOUTx T CONV Since the DAC conversion is implemented as pipelined procedure, a new conversion can be started after only 12 GCLK_DAC periods. Therefore if DATAx is written while a conversion is ongoing, start of conversion is postponed until DACx is ready to start next conversion.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter • The frequency of GCLK_DAC must be equal or lower than 12MHz (corresponding to 1MSPS). 47.6.4 DMA Operation In single mode (CTRLB.DIFF=0), DAC Controller generates the following DMA requests: • Data Buffer 0 Empty (EMPTY0): The request is set when data is transferred from DATABUF0 or DATA0 to the internal data buffer of DAC0.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the DAC Controller is reset. See 47.8.6 INTFLAG for details on how to clear interrupt flags.
PAGE 1679
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter If DACx conversion is stopped in standby sleep mode, DACx is also disabled to reduce power consumption. When exiting standby sleep mode, DACx is enabled again, therefore a certain startup time is required before starting a new conversion. DAC Controller is compatible with SleepWalking: if RUNSTDBY=1, when an input event (STARTx) is detected in sleep mode, the DAC Controller will request GCLK_DAC in order to complete the conversion. 47.6.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter The DAC can only maintain its output within one LSB of the desired value for approximately 100µs. When a DAC is used to generate a static voltage or at a rate less than 20kSPS, the conversion must be refreshed periodically. The OSCULP32K clock can start new conversions automatically after a specified period. Write a value to the Refresh bit field in the DAC Control x register (DACCTRLx.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.6.9.5 Dithering Mode Dithering is enabled by setting DACCTRLx.DITHER to 1. In dithering mode, DATAx is a 16-bit unsigned value where DATAx[15:4] is the 12-bit data converted by DAC and DATAx[3:0] represent the dither bits, used to minimize the quantization error.
PAGE 1682
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Figure 47-6. Interpolator Spectral Mask for 2x OSR 0 -24 -2.4 gain (dB), 0–fs/2 mask gain (dB), overall mask 3rd order SINC filter overall mask for OSR = 2 0 -48 -72 -96 -120 3rd order SINC filter 0–fs/2 mask for OSR = 2 -4.8 -7.2 -9.6 0 0.125*fs 0.25*fs 0.375*fs 0.5*fs 0.625*fs frequency (Hz), overall mask 0.75*fs 0.
PAGE 1683
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Figure 47-9. Interpolator Spectral Mask for 16x OSR 0 -24 -2.4 gain (dB), 0–fs/2 mask gain (dB), overall mask 3rd order SINC filter overall mask for OSR = 16 0 -48 -72 -96 -120 3rd order SINC filter 0–fs/2 mask for OSR = 16 -4.8 -7.2 -9.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.7 Register Summary Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 47.6.8 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 Access Reset 2 1 0 ENABLE SWRST R/W R/W 0 0 Bit 1 – ENABLE Enable DAC Controller Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.
PAGE 1687
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.2 Control B Name: Offset: Reset: Property: Bit 7 CTRLB 0x01 0x02 PAC Write-Protection 6 5 4 3 2 1 REFSEL[1:0] Access Reset 0 DIFF R/W R/W R/W 0 1 0 Bits 2:1 – REFSEL[1:0] Reference Selection This bit field selects the Reference Voltage for both DACs.
PAGE 1688
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.3 Event Control Name: Offset: Reset: Property: Bit Access Reset EVCTRL 0x02 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 RESRDYEO1 RESRDYEO0 INVEI1 INVEI0 EMPTYEO1 EMPTYEO0 STARTEI1 STARTEI0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – RESRDYEO1 Enable Result Ready of Filter 1 output event This bit controls whether the RESRDY1 Event is enabled when the interpolated data is ready.
PAGE 1689
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Bit 1 – STARTEI1 Start Conversion Event Input DAC1 This bit indicates if the Start input event for DAC1 is enabled. Value Description 0 A new conversion will not be triggered on any incoming event. 1 A new conversion will be triggered on any incoming event. Bit 0 – STARTEI0 Start Conversion Event Input DAC0 This bit indicates if the Start input event for DAC0 is enabled.
PAGE 1690
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x04 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 1691
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Writing a '1' to this bit will clear the Data Buffer 1 Empty Interrupt Enable bit, which disables the Data Buffer 1 Empty interrupt. Value Description 0 The Data Buffer 1 Empty interrupt is disabled. 1 The Data Buffer 1 Empty interrupt is enabled. Bit 2 – EMPTY0 Data Buffer 0 Empty Interrupt Enable Writing a '0' to this bit has no effect.
PAGE 1692
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x05 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 1693
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Writing a '1' to this bit will set the Data Buffer 1 Empty Interrupt Enable bit, which enables the Data Buffer 1 Empty interrupt. Value Description 0 The Data Buffer 1 Empty interrupt is disabled. 1 The Data Buffer 1 Empty interrupt is enabled. Bit 2 – EMPTY0 Data Buffer 0 Empty Interrupt Enable Writing a '0' to this bit has no effect.
PAGE 1694
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit Access Reset INTFLAG 0x06 0x00 - 7 6 5 4 3 2 1 0 OVERRUN1 OVERRUN0 RESRDY1 RESRDY0 EMPTY1 EMPTY0 UNDERRUN1 UNDERRUN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – OVERRUN1 Overrun for Filter Channel 1 This flag is set when the DMA is not cleared while the RESULT1 register gets new data. Writing a '0' to this bit has no effect.
PAGE 1695
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Bit 1 – UNDERRUN1 DAC1 Underrun This flag is cleared by writing a '1' to it. This flag is set when a start conversion event (START1) occurred before new data is copied/written to the DAC1 data buffer and will generate an interrupt request if INTENCLR/INTENSET.UNDERRUN1=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the DAC1 Underrun interrupt flag.
PAGE 1696
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.7 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x07 0x00 - 6 5 4 3 2 1 0 EOC1 EOC0 READY1 READY0 Access R R R R Reset 0 0 0 0 Bit 3 – EOC1 DAC1 End of Conversion This bit is cleared when DATA1 register is written. Value Description 0 No conversion completed since last load of DATA1. 1 DAC1 conversion is complete, VOUT1 is stable.
PAGE 1697
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.8 Synchronization Busy Name: Offset: Reset: Property: Bit SYNCBUSY 0x08 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Access Reset Bit Access Reset Bit Access Reset Bit 5 4 3 2 1 0 DATABUF1 DATABUF0 DATA1 DATA0 ENABLE SWRST Access R R R R R R Reset 0 0 0 0 0 0 Bit 5 – DATABUF1 Data Buffer DAC1 This bit is set when DATABUF1 register is written.
PAGE 1698
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Bit 2 – DATA0 Data DAC0 This bit is set when DATA0 register is written. This bit is cleared when DATA0 synchronization is completed. Value Description 0 No ongoing synchronized access. 1 Synchronized access is ongoing. Bit 1 – ENABLE DAC Enable Status This bit is set when CTRLA.ENABLE bit is written. This bit is cleared when CTRLA.ENABLE synchronization is completed. Value Description 0 No ongoing synchronization. 1 Synchronization is ongoing.
PAGE 1699
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.
PAGE 1700
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Value 1 Description The filter is used as standalone Bits 3:2 – CCTRL[1:0] Current Control This field defines the current in output buffer according to conversion rate. Current Control Value Name Description 0x0 CC100K GCLK_DAC ≤ 1.2MHz (100kSPS) 0x1 CC1M 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) 0x2 CC12M 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) 0x3 Reserved Bit 1 – ENABLE Enable DAC0 This bit enables DAC0 when DAC Controller is enabled (CTRLA.ENABLE).
PAGE 1701
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.
PAGE 1702
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter Value 1 Description The filter is used as standalone Bits 3:2 – CCTRL[1:0] Current Control This field defines the current in output buffer. Current Control Value Name Description 0x0 CC100K GCLK_DAC <= 1.2MHz (100kSPS) 0x1 CC1M 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) 0x2 CC12M 6MHz < GCLK_DAC <= 12MHz (1MSPS) 0x3 Reserved Bit 1 – ENABLE Enable DAC1 This bit enables DAC1 when DAC Controller is enabled (CTRLA.ENABLE).
PAGE 1703
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.11 Data DAC0 Name: Offset: Reset: Property: DATA0 0x10 0x0000 PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 Access W W W W Reset 0 0 W W W W 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[15:8] DATA[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – DATA[15:0] DAC0 Data DATA0 register contains the 12-bit value that is converted to a voltage by the DAC0.
PAGE 1704
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.12 Data DAC1 Name: Offset: Reset: Property: DATA1 0x12 0x0000 PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 Access W W W W Reset 0 0 W W W W 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[15:8] DATA[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – DATA[15:0] DAC1 Data DATA1 register contains the 12-bit value that is converted to a voltage by the DAC1.
PAGE 1705
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.13 Data Buffer DAC0 Name: Offset: Reset: Property: DATABUF0 0x14 0x0000 Write-Synchronized Bit 15 14 13 12 Access W W W W Reset 0 0 0 0 Bit 7 6 5 4 11 10 9 8 W W W W 0 0 0 0 3 2 1 0 DATABUF[15:8] DATABUF[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – DATABUF[15:0] DAC0 Data Buffer DATABUF0 contains the value to be transferred into DATA0 when a START0 event occurs.
PAGE 1706
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.14 Data Buffer DAC1 Name: Offset: Reset: Property: DATABUF1 0x16 0x0000 Write-Synchronized Bit 15 14 13 12 Access W W W W Reset 0 0 0 0 Bit 7 6 5 4 11 10 9 8 W W W W 0 0 0 0 3 2 1 0 DATABUF[15:8] DATABUF[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – DATABUF[15:0] DAC1 Data Buffer DATABUF1 contains the value to be transferred into DATA1 when a START1 event occurs.
PAGE 1707
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.15 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x18 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bits controls the functionality when the CPU is halted by an external debugger. Value Description 0 The DAC is halted when the CPU is halted by an external debugger. Any ongoing conversion will complete.
PAGE 1708
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.
PAGE 1709
SAM D5x/E5x Family Data Sheet DAC – Digital-to-Analog Converter 47.8.
PAGE 1710
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48. TC – Timer/Counter 48.1 Overview There are up to eight TC peripheral instances. Each TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events or IO pin edges, allowing for capturing of frequency and/or pulse width.
PAGE 1711
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.3 Block Diagram Figure 48-1. Timer/Counter Block Diagram Base Counter BUFV PERBUF Prescaler PER "count" Counter OVF (INT/Event/DMA Req.) "clear" "load" COUNT ERR (INT Req.) Control Logic "direction" TC Input Event Event System "event" BOTTOM =0 UPDATE TOP = Compare/Capture (Unit x = {0,1} BUFV "capture" CCBUFx Control Logic WO[1] CCx Waveform Generation "match" = 48.4 WO[0] MCx (INT/Event/DMA Req.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter Related Links 6. I/O Multiplexing and Considerations 48.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 48.5.1 I/O Lines In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT). Table 48-2. I/O Lines Instance Signal I/O Line Peripheral Function MODULE0 SIGNAL PAxx A Related Links 32.
PAGE 1713
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links 10.2 Nested Vector Interrupt Controller 48.5.6 Events The events of this peripheral are connected to the Event System. Related Links 31. EVSYS – Event System 48.5.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter Table 48-3. Timer/Counter Definitions Name Description TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be the same as Period (PER) or the Compare Channel 0 (CC0) register value depending on the waveform generator mode in 48.6.2.6.1 Waveform Output Operations.
PAGE 1715
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.6.2 Basic Operation 48.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the TC is disabled (CTRLA.ENABLE =0): • • • • Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits Drive Control register (DRVCTRL) Wave register (WAVE) Event Control register (EVCTRL) Writing to Enable-Protected bits and setting the CTRLA.
PAGE 1716
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER). Note: When counting events, the prescaler is bypassed. The joint stream of prescaler ticks and event action ticks is called CLK_TC_CNT. Figure 48-2. Prescaler PRESCALER GCLK_TC Prescaler EVACT GCLK_TC / {1,2,4,8,64,256,1024} CLK_TC_CNT COUNT EVENT 48.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-3. Counter Operation Period (T) Direction Change COUNT written MAX "reload" update "clear" update COUNT TOP ZERO DIR Due to asynchronous clock domains, the internal counter settings are written when the synchronization is complete. Normal operation must be used when using the counter as timer base for the capture channels. 48.6.2.5.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.6.2.6 Compare Operations By default, the Compare/Capture channel is configured for compare operations. When using the TC and the Compare/Capture Value registers (CCx) for compare operations, the counter value is continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation. The Channel x Compare Buffer (CCBUFx) registers provide double buffer capability.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-4. Normal Frequency Operation Period (T) Direction Change COUNT Written MAX COUNT "reload" update "clear" update "match" TOP CCx ZERO WO[x] Match Frequency Generation (MFRQ) For Match Frequency Generation, the period time (T) is controlled by the CC0 register instead of PER or MAX. WO[0] toggles on each Update condition. Figure 48-5.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-6. Match PWM Operation Period(T) CCx= Zero CCx= TOP " clear" update " match" MAX CC0 COUNT CC1 ZERO WO[1] The table below shows the Update Counter and Overflow Event/Interrupt Generation conditions in different operation modes. Table 48-4.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-7. Compare Channel Double Buffering "write enable" CCBUFVx UPDATE "data write" EN CCBUFx EN CCx COUNT = "match" Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are available in the I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing a '1' to CTRLBSET.LUPD. Note: In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.
PAGE 1722
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-9. Unbuffered Single-Slope Down-Counting Operation MAX "reload" update "write" COUNT ZERO New TOP written to PER that is higher than current COUNT New TOP written to PER that is lower than current COUNT When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation. The period register is always updated on the update condition, as shown in Figure 48-10.
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SAM D5x/E5x Family Data Sheet TC – Timer/Counter • When the channel is counting events from the Event System, write a '1' to the TC Event Input Invert Enable bit in Event Control register (EVCTRL.TCINV). Figure 48-11. Capture Double Buffering "capture" COUNT BV EN CCBx IF EN CCx "INT/DMA request" data read For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read, any content in CCBUFx is transferred to CCx.
PAGE 1724
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.6.2.8.2 Period and Pulse-Width (PPW) Capture Action The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure the pulse width and period and to characterize the frequency f and duty cycle of an input signal: �= 1 � dutyCycle = �� Figure 48-13.
PAGE 1725
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-14. Pulse-Width Capture on Channel 0 external signal Pulsewitdh (tp) events MAX "capture" "restart" COUNT ZERO CC0 CC0 The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. 48.6.3 Additional Features 48.6.3.
PAGE 1726
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-15. Time-Stamp Capture Events MAX TOP "capture" "overflow" COUNT ZERO CCx Value COUNT COUNT TOP COUNT MAX 48.6.3.3 Minimum Capture The minimum capture is enabled by writing the CAPTMIN mode in the Channel n Capture Mode bits in the Control A register (CTRLA.CAPTMODEn = CAPTMIN). CCx Content: In CAPTMIN operations, CCx keeps the Minimum captured values.
PAGE 1727
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Figure 48-16. Maximum Capture Operation with CC0 Initialized with ZERO Value TOP COUNT "clear" update "match" CC0 ZERO Input event CC0 Event/ Interrupt 48.6.4 DMA Operation The TC can generate the following DMA requests: • Overflow (OVF): the request is set when an update condition (overflow, underflow or re-trigger) is detected, the request is cleared by hardware on DMA acknowledge.
PAGE 1728
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the corresponding output event. The output event is disabled by writing EVCTRL.MCEOx=0. One of the following event actions can be selected by the Event Action bit group in the Event Control register (EVCTRL.
PAGE 1729
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Required read synchronization is denoted by the "Read-Synchronized" property in the register description. 48.7 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
PAGE 1730
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1 Offset Register Summary - 8-bit Mode Name Bit Pos.
PAGE 1731
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.
PAGE 1732
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Bits 16, 17 – CAPTENx Capture Channel x Enable Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel. These bits are not synchronized. Value Description 0 CAPTEN disables capture on channel x. 1 CAPTEN enables capture on channel x. Bit 15 – DMAOS DMA One-Shot Trigger Mode This bit enables the DMA One-shot Trigger Mode. Writing a '1' to this bit will generate a DMA trigger on TC cycle following a TC_CTRLBSET_CMD_DMAOS command.
PAGE 1733
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 0 1 Description The TC is halted in standby. The TC continues to run in standby. Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler. These bits are not synchronized.
PAGE 1734
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.2 Control B Clear Name: Offset: Reset: Property: CTRLBCLR 0x04 0x00 PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET).
PAGE 1735
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). © 2019 Microchip Technology Inc.
PAGE 1736
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.3 Control B Set Name: Offset: Reset: Property: CTRLBSET 0x05 0x00 PAC Write-Protection, Read-synchronized, Write-Synchronized This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR).
PAGE 1737
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 1 Description The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. Bit 0 – DIR Counter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect Writing a '1' to this bit will clear the bit and make the counter count up. Value Description 0 The timer/counter is counting up (incrementing). 1 The timer/counter is counting down (decrementing).
PAGE 1738
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.4 Event Control Name: Offset: Reset: Property: Bit 15 EVCTRL 0x06 0x0000 PAC Write-Protection, Enable-Protected 14 Access Reset Bit 7 6 Access Reset 13 12 MCEO1 MCEO0 11 OVFEO R/W R/W R/W 0 0 0 5 4 TCEI TCINV R/W R/W R/W R/W R/W 0 0 0 0 0 3 10 2 9 1 8 0 EVACT[2:0] Bit 13 – MCEO1 Match or Capture Channel x Event Output Enable [x = 1..
PAGE 1739
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 1 Description Input event source is inverted. Bits 2:0 – EVACT[2:0] Event Action These bits define the event action the TC will perform on an event.
PAGE 1740
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.5 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x08 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 1741
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.6 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x09 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 1742
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.7 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x0A 0x00 - 6 Access Reset 5 4 1 0 MC1 MC0 3 2 ERR OVF R/W R/W R/W R/W 0 0 0 0 Bit 5 – MC1 Match or Capture Channel x This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value.
PAGE 1743
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.8 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x0B 0x01 Read-Synchronized 6 Access Reset 5 4 3 1 0 CCBUFV1 CCBUFV0 PERBUFV 2 SLAVE STOP R/W R/W R/W R R 0 0 0 0 1 Bits 4, 5 – CCBUFV Channel x Compare or Capture Buffer Valid For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register. The bit x is cleared by writing a '1' to it when CTRLB.
PAGE 1744
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.9 Waveform Generation Control Name: Offset: Reset: Property: Bit 7 WAVE 0x0C 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 2 1 0 WAVEGEN[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – WAVEGEN[1:0] Waveform Generation Mode These bits select the waveform generation operation. They affect the top value, as shown in 48.6.2.6.1 Waveform Output Operations. They also control whether frequency or PWM waveform generation should be used.
PAGE 1745
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.10 Driver Control Name: Offset: Reset: Property: Bit 7 DRVCTRL 0x0D 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 Access Reset 2 1 0 INVEN1 INVEN0 R/W R/W 0 0 Bits 0, 1 – INVENx Output Waveform x Invert Enable Bit x of INVEN[1:0] selects inversion of the output or capture trigger input of channel x. Value Description 0 Disable inversion of the WO[x] output and IO input pin.
PAGE 1746
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.11 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0F 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Run in Debug Mode This bit is not affected by a software Reset, and should not be changed by software while the TC is enabled. Value Description 0 The TC is halted when the device is halted in debug mode. 1 The TC continues normal operation when the device is halted in debug mode.
PAGE 1747
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.
PAGE 1748
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Bit 0 – SWRST SWRST Synchronization Busy This bit is cleared when the synchronization of SWRST bit between the clock domains is complete. This bit is set when the synchronization of SWRST bit between clock domains is started. © 2019 Microchip Technology Inc.
PAGE 1749
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.13 Counter Value, 8-bit Mode Name: Offset: Reset: Property: COUNT 0x14 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized Note: Prior to any read access, this register must be synchronized by user by writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
PAGE 1750
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.14 Period Value, 8-bit Mode Name: Offset: Reset: Property: Bit 7 PER 0x1B 0xFF Write-Synchronized 6 5 4 3 2 1 0 PER[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 1 Bits 7:0 – PER[7:0] Period Value These bits hold the value of the Period Buffer register PERBUF. The value is copied to PER register on UPDATE condition. © 2019 Microchip Technology Inc.
PAGE 1751
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.15 Channel x Compare/Capture Value, 8-bit Mode Name: Offset: Reset: Property: Bit 7 CCx 0x1C + x*0x01 [x=0..1] 0x00 Write-Synchronized, Read-Synchronized 6 5 4 3 2 1 0 CC[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – CC[7:0] Channel x Compare/Capture Value These bits contain the compare/capture value in 8-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (WAVE.
PAGE 1752
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.16 Period Buffer Value, 8-bit Mode Name: Offset: Reset: Property: Bit 7 PERBUF 0x2F 0xFF Write-Synchronized 6 5 4 3 2 1 0 PERBUF[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 1 Bits 7:0 – PERBUF[7:0] Period Buffer Value These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition. © 2019 Microchip Technology Inc.
PAGE 1753
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.1.17 Channel x Compare Buffer Value, 8-bit Mode Name: Offset: Reset: Property: Bit 7 CCBUFx 0x30 + x*0x01 [x=0..1] 0x00 Write-Synchronized 6 5 4 3 2 1 0 CCBUF[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – CCBUF[7:0] Channel x Compare Buffer Value These bits hold the value of the Channel x Compare Buffer Value. When the buffer valid flag is '1' and double buffering is enabled (CTRLBCLR.
PAGE 1754
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2 Offset Register Summary - 16-bit Mode Name Bit Pos.
PAGE 1755
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.
PAGE 1756
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Bits 16, 17 – CAPTENx Capture Channel x Enable Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel. These bits are not synchronized. Value Description 0 CAPTEN disables capture on channel x. 1 CAPTEN enables capture on channel x. Bit 15 – DMAOS DMA One-Shot Trigger Mode This bit enables the DMA One-shot Trigger Mode. Writing a '1' to this bit will generate a DMA trigger on TC cycle following a TC_CTRLBSET_CMD_DMAOS command.
PAGE 1757
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 0 1 Description The TC is halted in standby. The TC continues to run in standby. Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler. These bits are not synchronized.
PAGE 1758
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.2 Control B Clear Name: Offset: Reset: Property: CTRLBCLR 0x04 0x00 PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET).
PAGE 1759
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). © 2019 Microchip Technology Inc.
PAGE 1760
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.3 Control B Set Name: Offset: Reset: Property: CTRLBSET 0x05 0x00 PAC Write-Protection, Read-synchronized, Write-Synchronized This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR).
PAGE 1761
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 1 Description The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. Bit 0 – DIR Counter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect Writing a '1' to this bit will clear the bit and make the counter count up. Value Description 0 The timer/counter is counting up (incrementing). 1 The timer/counter is counting down (decrementing).
PAGE 1762
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.4 Event Control Name: Offset: Reset: Property: Bit 15 EVCTRL 0x06 0x0000 PAC Write-Protection, Enable-Protected 14 Access Reset Bit 7 6 Access Reset 13 12 MCEO1 MCEO0 11 OVFEO R/W R/W R/W 0 0 0 5 4 TCEI TCINV R/W R/W R/W R/W R/W 0 0 0 0 0 3 10 2 9 1 8 0 EVACT[2:0] Bit 13 – MCEO1 Match or Capture Channel x Event Output Enable [x = 1..
PAGE 1763
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 1 Description Input event source is inverted. Bits 2:0 – EVACT[2:0] Event Action These bits define the event action the TC will perform on an event.
PAGE 1764
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.5 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x08 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 1765
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.6 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x09 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 1766
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.7 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x0A 0x00 - 6 Access Reset 5 4 1 0 MC1 MC0 3 2 ERR OVF R/W R/W R/W R/W 0 0 0 0 Bit 5 – MC1 Match or Capture Channel x This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value.
PAGE 1767
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.8 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x0B 0x01 Read-Synchronized 6 Access Reset 5 4 3 1 0 CCBUFV1 CCBUFV0 PERBUFV 2 SLAVE STOP R/W R/W R/W R R 0 0 0 0 1 Bits 4, 5 – CCBUFV Channel x Compare or Capture Buffer Valid For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register. The bit x is cleared by writing a '1' to it when CTRLB.
PAGE 1768
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.9 Waveform Generation Control Name: Offset: Reset: Property: Bit 7 WAVE 0x0C 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 2 1 0 WAVEGEN[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – WAVEGEN[1:0] Waveform Generation Mode These bits select the waveform generation operation. They affect the top value, as shown in 48.6.2.6.1 Waveform Output Operations. They also control whether frequency or PWM waveform generation should be used.
PAGE 1769
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.10 Driver Control Name: Offset: Reset: Property: Bit 7 DRVCTRL 0x0D 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 Access Reset 2 1 0 INVEN1 INVEN0 R/W R/W 0 0 Bits 0, 1 – INVENx Output Waveform x Invert Enable Bit x of INVEN[1:0] selects inversion of the output or capture trigger input of channel x. Value Description 0 Disable inversion of the WO[x] output and IO input pin.
PAGE 1770
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.11 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0F 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Run in Debug Mode This bit is not affected by a software Reset, and should not be changed by software while the TC is enabled. Value Description 0 The TC is halted when the device is halted in debug mode. 1 The TC continues normal operation when the device is halted in debug mode.
PAGE 1771
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.
PAGE 1772
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Bit 0 – SWRST SWRST Synchronization Busy This bit is cleared when the synchronization of SWRST bit between the clock domains is complete. This bit is set when the synchronization of SWRST bit between clock domains is started. © 2019 Microchip Technology Inc.
PAGE 1773
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.13 Counter Value, 16-bit Mode Name: Offset: Reset: Property: COUNT 0x14 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized Note: Prior to any read access, this register must be synchronized by user by writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
PAGE 1774
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.14 Channel x Compare/Capture Value, 16-bit Mode Name: Offset: Reset: Property: Bit 15 CCx 0x1C + x*0x02 [x=0..
PAGE 1775
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.2.15 Channel x Compare Buffer Value, 16-bit Mode Name: Offset: Reset: Property: Bit 15 CCBUFx 0x30 + x*0x02 [x=0..
PAGE 1776
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3 Offset Register Summary - 32-bit Mode Name Bit Pos.
PAGE 1777
SAM D5x/E5x Family Data Sheet TC – Timer/Counter ...........continued Offset 0x34 Name CCBUF1 Bit Pos. 7:0 CCBUF[7:0] 15:8 CCBUF[15:8] 23:16 CCBUF[23:16] 31:24 CCBUF[31:24] © 2019 Microchip Technology Inc.
PAGE 1778
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.
PAGE 1779
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Bits 16, 17 – CAPTENx Capture Channel x Enable Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel. These bits are not synchronized. Value Description 0 CAPTEN disables capture on channel x. 1 CAPTEN enables capture on channel x. Bit 15 – DMAOS DMA One-Shot Trigger Mode This bit enables the DMA One-shot Trigger Mode. Writing a '1' to this bit will generate a DMA trigger on TC cycle following a TC_CTRLBSET_CMD_DMAOS command.
PAGE 1780
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 0 1 Description The TC is halted in standby. The TC continues to run in standby. Bits 5:4 – PRESCSYNC[1:0] Prescaler and Counter Synchronization These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler. These bits are not synchronized.
PAGE 1781
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.2 Control B Clear Name: Offset: Reset: Property: CTRLBCLR 0x04 0x00 PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET).
PAGE 1782
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). © 2019 Microchip Technology Inc.
PAGE 1783
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.3 Control B Set Name: Offset: Reset: Property: CTRLBSET 0x05 0x00 PAC Write-Protection, Read-synchronized, Write-Synchronized This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR).
PAGE 1784
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 1 Description The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. Bit 0 – DIR Counter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect Writing a '1' to this bit will clear the bit and make the counter count up. Value Description 0 The timer/counter is counting up (incrementing). 1 The timer/counter is counting down (decrementing).
PAGE 1785
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.4 Event Control Name: Offset: Reset: Property: Bit 15 EVCTRL 0x06 0x0000 PAC Write-Protection, Enable-Protected 14 Access Reset Bit 7 6 Access Reset 13 12 MCEO1 MCEO0 11 OVFEO R/W R/W R/W 0 0 0 5 4 TCEI TCINV R/W R/W R/W R/W R/W 0 0 0 0 0 3 10 2 9 1 8 0 EVACT[2:0] Bit 13 – MCEO1 Match or Capture Channel x Event Output Enable [x = 1..
PAGE 1786
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Value 1 Description Input event source is inverted. Bits 2:0 – EVACT[2:0] Event Action These bits define the event action the TC will perform on an event.
PAGE 1787
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.5 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x08 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 1788
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.6 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x09 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 1789
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.7 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x0A 0x00 - 6 Access Reset 5 4 1 0 MC1 MC0 3 2 ERR OVF R/W R/W R/W R/W 0 0 0 0 Bit 5 – MC1 Match or Capture Channel x This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value.
PAGE 1790
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.8 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x0B 0x01 Read-Synchronized 6 Access Reset 5 4 3 1 0 CCBUFV1 CCBUFV0 PERBUFV 2 SLAVE STOP R/W R/W R/W R R 0 0 0 0 1 Bits 4, 5 – CCBUFV Channel x Compare or Capture Buffer Valid For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register. The bit x is cleared by writing a '1' to it when CTRLB.
PAGE 1791
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.9 Waveform Generation Control Name: Offset: Reset: Property: Bit 7 WAVE 0x0C 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 2 1 0 WAVEGEN[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – WAVEGEN[1:0] Waveform Generation Mode These bits select the waveform generation operation. They affect the top value, as shown in 48.6.2.6.1 Waveform Output Operations. They also control whether frequency or PWM waveform generation should be used.
PAGE 1792
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.10 Driver Control Name: Offset: Reset: Property: Bit 7 DRVCTRL 0x0D 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 Access Reset 2 1 0 INVEN1 INVEN0 R/W R/W 0 0 Bits 0, 1 – INVENx Output Waveform x Invert Enable Bit x of INVEN[1:0] selects inversion of the output or capture trigger input of channel x. Value Description 0 Disable inversion of the WO[x] output and IO input pin.
PAGE 1793
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.11 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0F 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Run in Debug Mode This bit is not affected by a software Reset, and should not be changed by software while the TC is enabled. Value Description 0 The TC is halted when the device is halted in debug mode. 1 The TC continues normal operation when the device is halted in debug mode.
PAGE 1794
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.
PAGE 1795
SAM D5x/E5x Family Data Sheet TC – Timer/Counter Bit 0 – SWRST SWRST Synchronization Busy This bit is cleared when the synchronization of SWRST bit between the clock domains is complete. This bit is set when the synchronization of SWRST bit between clock domains is started. © 2019 Microchip Technology Inc.
PAGE 1796
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.13 Counter Value, 32-bit Mode Name: Offset: Reset: Property: COUNT 0x14 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized Note: Prior to any read access, this register must be synchronized by user by writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
PAGE 1797
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.14 Channel x Compare/Capture Value, 32-bit Mode Name: Offset: Reset: Property: Bit 31 CCx 0x1C + x*0x04 [x=0..
PAGE 1798
SAM D5x/E5x Family Data Sheet TC – Timer/Counter 48.7.3.15 Channel x Compare Buffer Value, 32-bit Mode Name: Offset: Reset: Property: Bit 31 CCBUFx 0x30 + x*0x04 [x=0..
PAGE 1799
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49. TCC – Timer/Counter for Control Applications 49.1 Overview The device provides five instances of the Timer/Counter for Control applications (TCC) peripheral, TCC[4:0]. Each TCC instance consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events or clock pulses.
PAGE 1800
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications – Two non-recoverable fault sources – Debugger can be a source of non-recoverable fault • Input Events: – Two input events (EVx) for counter – One input event (MCx) for each channel • Output Events: – Three output events (Count, re-trigger and overflow) are available for counter – One compare match/input capture event output for each channel • Interrupts: – Overflow and re-trigger interrupt – Compare match/input capture interrupt – I
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications ...........continued Pin Name Type Description … ... ... TCC/WO[WO_NUM-1] Digital output Compare channel n waveform output Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 6. I/O Multiplexing and Considerations 49.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links 10.2 Nested Vector Interrupt Controller 49.5.6 Events The events of this peripheral are connected to the Event System. Related Links 31. EVSYS – Event System 49.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Table 49-1. Timer/Counter for Control Applications - Definitions Name Description TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be the same as Period (PER) or the Compare Channel 0 (CC0) register value depending on the Waveform Generator mode in 49.6.2.5.1 Waveform Output Generation Operations. ZERO The counter reaches ZERO when it contains all zeroes.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications • • • • • Recoverable faults and non-recoverable faults Output matrix Dead-time insertion Swap Pattern generation See also Figure 49-1. The output matrix (OTMX) can distribute and route out the TCC waveform outputs across the port pins in different configurations, each optimized for different application types.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Optionally, the following configurations can be set before enabling TCC: 1. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER). 2. Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC). 3. If down-counting operation is desired, write the Counter Direction bit in the Control B Set register (CTRLBSET.DIR) to '1'. 4. Select the Waveform Generation operation in the WAVE register (WAVE.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications The counter will count up or down for each tick (clock or event) until it reaches TOP or ZERO. When it's counting up and TOP is reached, the counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF) will be set. When down-counting, the counter is reloaded with the TOP value when ZERO is reached (underflow), and INTFLAG.OVF is set. INTFLAG.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). The Re-Trigger bit in the Interrupt Flag Status and Clear register will be set (INTFLAG.TRG). It is also possible to generate an event by writing a '1' to the Re-Trigger Event Output Enable bit in the Event Control register (EVCTRL.TRGEO).
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications overridden according to the Driver Control register settings (DRVCTRL.NREx and DRVCTRL.NRVx). TCE0 and TCE1 must be configured as asynchronous events. Event Action Off If the event action is disabled (EVCTRL.EVACTn=0x0, OFF), enabling the counter will also start the counter. Related Links 49.6.3.1 One-Shot Operation 49.6.2.5 Compare Operations By default, the Compare/Capture channel is configured for compare operations.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform operations, the TOP value is defined by the Period (PER) register value. For dual-slope waveform operations, the update time occurs when the counter reaches ZERO. For the other Waveforms Generation modes, the update time occurs on counter wraparound, on overflow, underflow, or re-trigger.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-4. Normal Frequency Operation Period (T) Direction Change COUNT Written MAX COUNT "reload" update "clear" update "match" TOP CCx ZERO WO[x] 49.6.2.5.3 Match Frequency (MFRQ) For Match Frequency generation, the period time (T) is controlled by CC0 register instead of PER. WO[0] toggles on each update condition. Figure 49-5.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform: �PWM_SS = log(TOP+1) log(2) �PWM_SS = �GCLK_TCC N(TOP+1) The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation: Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). 49.6.2.5.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications N represents the prescaler divider used. Note: In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2, the CCx MSB bit defines the ramp on which the CCx Match interrupt or event is generated. (Rising if CCx[MSB] = 0, falling if CCx[MSB] = 1.) Related Links 49.6.3.2 Circular Buffer 49.6.2.5.7 Dual-Slope Critical PWM Generation Critical mode generation allows generation of non-aligned centered pulses.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output. 49.6.2.6 Double Buffering The Pattern (PATT), Period (PER) and Compare Channels (CCx) registers are all double buffered.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-10. Unbuffered Single-Slope Up-Counting Operation Counter Wraparound MAX "clear" update "write" COUNT ZERO New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT Figure 49-11.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-13. Changing the Period Using Buffering MAX "reload" update "write" COUNT ZERO New value written to PERBUF that is higher than current COUNT New value written to PERBUF that is lower than current COUNT PER is updated with PERBUF value 49.6.2.7 Capture Operations To enable and use capture operations, the Match or Capture Channel x Event Input Enable bit in the Event Control register (EVCTRL.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-15. Capture Double Buffering "capture" COUNT BUFV EN CCBUFx IF EN CCx "INT/DMA request" data read The TCC can detect capture overflow of the input capture channels. When a new capture event is detected while the Capture Buffer Valid flag (STATUS.CCBUFV) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications The corresponding capture is done only if the channel is enabled in Capture mode (CTRLA.CPTENx=1). If not, the capture action will be ignored and the channel will be enabled in compare mode of operation. When only one of these channel is required, the other channel can be used for other purposes. The TCC can detect capture overflow of the input capture channels. When a new capture event is detected while the INTFLAG.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, and can improve the accuracy of the average output pulse width and period. The extra clock cycles are added on some of the compare match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither patterns.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications DITH5 mode: ��ℎ = DITHERCY 1 + CCx 32 �GCLK_TCC ��ℎ = DITHERCY 1 + CCx 64 �GCLK_TCC DITH6 mode: Note: The PWM period will remain static in this case. 49.6.3.4 Ramp Operations Three ramp operation modes are supported. All of them require the timer/counter running in single-slope PWM generation. The Ramp mode is selected by writing to the Ramp Mode bits in the Waveform Control register (WAVE.RAMP).
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Alternate RAMP2 (RAMP2A) Operation Alternate RAMP2 operation is similar to RAMP2, but CC0 controls both WO[0] and WO[1] waveforms when the corresponding circular buffer option is enabled (CIPEREN=1). The waveform polarity is the same on both outputs. Channel 1 can be used in capture mode. Figure 49-19.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-21. RAMP2 Critical Operation With 2 Channels Ramp A B A TOP CC0 B Retrigger on FaultA CC1 COUNT "clear" update "match" TOP CC1 ZERO WO[0] POL0 = 0 WO[1] Keep on FaultB POL1 = 1 FaultA input FaultB input 49.6.3.5 Recoverable Faults Recoverable faults can restart or halt the timer/counter.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 1 + BLANKVAL �GCLK_TCCx_PRESC Here, fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency fGCLK_TCCx. �� = The prescaler is enabled by writing '1' to the Fault n Blanking Prescaler bit (FCTRLn.BLANKPRESC). When disabled, fGCLK_TCCx_PRESC=fGCLK_TCCx. When enabled, fGCLK_TCCx_PRESC=fGCLK_TCCx/64. The maximum blanking time (FCTRLn.BLANKVAL= 255) at fGCLK_TCCx=96MHz is 2.67µs (no prescaler) or 170µs (prescaling).
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-24.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-26. Waveform Generation in RAMP1 mode with Restart Action MAX "clear" update "match" TOP CC0 COUNT CC1 ZERO Restart Restart Fault Input A WO[0] WO[1] Figure 49-27.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications CCx Content: In CAPTMIN and CAPTMAX operations, CCx keeps the respective extremum captured values, see Figure 49-28. In LOCMIN, LOCMAX or DERIV0 operation, CCx follows the counter value at fault time, see Figure 49-29. Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding CCx register value to a value different from zero (for CAPTMIN) top (for CAPTMAX).
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-29. Capture Action “DERIV0” TOP COUNT "update" "match" CC0 ZERO WO[0] FaultA Input CC0 Event/ Interrupt Hardware This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n Halt Action Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is extended as long as the corresponding fault is present.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-31. Waveform Generation with Fault Qualification, Halt, and Restart Actions MAX "update" "match" TOP CC0 COUNT HALT ZERO Resume Fault A Input Qual -  - -  -  x  x - x Fault Input A KEEP WO[0] Software Halt Action This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n configuration register (FCTRLn.HALT).
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications (DRVCTRL.FILTERVALn). Therefore, the event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles. When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug operation.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-34. Waveform Extension Stage Details WEX OTMX PORTS DTI SWAP OTMX[x+WO_NUM/2] PATTERN PGV[x+WO_NUM/2] P[x+WO_NUM/2] LS OTMX DTIx PGO[x+WO_NUM/2] DTIxEN INV[x+WO_NUM/2] SWAPx PGO[x] HS INV[x] P[x] OTMX[x] PGV[x] The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations in the following table. Table 49-4.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications ...........continued Value OTMX[3] OTMX[2] OTMX[1] OTMX[0] 0x2 CC0 CC0 CC0 CC0 0x3 CC1 CC1 CC1 CC0 The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side (HS) of the wave generator output forced at low level. This OFF time is called dead time. Deadtime insertion ensures that the LS and HS will never switch simultaneously.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-36. Dead-Time Generator Timing Diagram "dti_cnt" T tP tDTILS t DTIHS "OTMX output" "DTLS" "DTHS" The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC), stepper motors, and full bridge control. See also Figure 49-37. Figure 49-37.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.6.5 DMA, Interrupts, and Events Table 49-6.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Counter overflow (OVF) If the One-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0', the TCC generates a DMA request on each cycle when an update condition (Overflow, Underflow or Re-trigger) is detected. When an update condition (Overflow, Underflow or Re-trigger) is detected while CTRLA.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Figure 49-38. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled Ramp A Cycle B A B A B N-1 N-2 N "update" COUNT ZERO STATUS.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications • • • • • • • Count (CNT) - refer also to description of EVCTRL.CNTSEL. Capture Overflow Error (ERR) Non-Recoverable Update Fault (UFS) Debug Fault State (DFS) Recoverable Faults (FAULTn) Non-recoverable Faults (FAULTx) Compare Match or Capture Channels (MCx) These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep Mode Controller section for details.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications • Count on event (increment or decrement, depending on counter direction) • Counter start - start counting on the event rising edge. Further events will not restart the counter; the counter will keep on counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO, depending on the direction. • Counter increment on event. This will increment the counter, irrespective of the counter direction.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications • Period Value and Period Buffer Value registers (PER and PERBUF) • Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. Required read synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links 13.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.7 Offset Register Summary Name Bit Pos. 7:0 RESOLUTION[1:0] 15:8 MSYNC 23:16 DMAOS ALOCK ENABLE PRESCYNC[1:0] RUNSTDBY SWRST PRESCALER[2:0] 0x00 CTRLA CPTEN2 CPTEN1 CPTEN0 0x04 CTRLBCLR 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR 0x05 CTRLBSET 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR 31:24 CPTEN5 CPTEN4 CPTEN3 0x06 ...
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications ...........continued Offset Name Bit Pos.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications ...........continued Offset Name Bit Pos. 7:0 0x50 CC3 CC[1:0] DITHER[5:0] 15:8 CC[9:2] 23:16 CC[17:10] 31:24 7:0 0x54 CC4 CC[1:0] DITHER[5:0] 15:8 CC[9:2] 23:16 CC[17:10] 31:24 7:0 0x58 CC5 CC[1:0] DITHER[5:0] 15:8 CC[9:2] 23:16 CC[17:10] 31:24 0x5C ... Reserved 0x63 0x64 PATTBUF 7:0 PGEB0[7:0] 15:8 PGVB0[7:0] 0x66 ...
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications ...........continued Offset Name Bit Pos. 7:0 0x84 CCBUF5 CCBUF[1:0] DITHERBUF[5:0] 15:8 CCBUF[9:2] 23:16 CCBUF[17:10] 31:24 49.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Value 0 1 Description The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/ underflow, and re-trigger events CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event. Bits 13:12 – PRESCYNC[1:0] Prescaler and Counter Synchronization These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on the next prescaled GCLK_TCCx clock.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Table 49-7. Dithering Value Name Description 0x0 NONE The dithering is disabled. 0x1 DITH4 Dithering is done every 16 PWM frames. PER[3:0] and CCx[3:0] contain dithering pattern selection. 0x2 DITH5 Dithering is done every 32 PWM frames. PER[4:0] and CCx[4:0] contain dithering pattern selection. 0x3 DITH6 Dithering is done every 64 PWM frames. PER[5:0] and CCx[5:0] contain dithering pattern selection.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.2 Control B Clear Name: Offset: Reset: Property: CTRLBCLR 0x04 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Value 1 Description The TCC will stop counting on the next underflow/overflow condition. Bit 1 – LUPD Lock Update This bit controls the update operation of the TCC buffered registers. When CTRLB.LUPD is cleared, the hardware UPDATE registers with value from their buffered registers is enabled. This bit has no effect when input capture operation is enabled. Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.3 Control B Set Name: Offset: Reset: Property: CTRLBSET 0x05 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBCLR) register.
PAGE 1848
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bit 1 – LUPD Lock Update This bit controls the update operation of the TCC buffered registers. When CTRLB.LUPD is set, the hardware UPDATE registers with value from their buffered registers is disabled. Disabling the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
PAGE 1850
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bit 4 – COUNT COUNT Synchronization Busy This bit is cleared when the synchronization of COUNT register between the clock domains is complete. This bit is set when the synchronization of COUNT register between clock domains is started. Bit 3 – STATUS STATUS Synchronization Busy This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.5 Fault Control A and B Name: Offset: Reset: Property: Bit FCTRLA, FCTRLB 0x0C + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Table 49-8. Fault n Capture Action Value Name 0x0 DISABLE 0x1 CAPT 0x2 CAPTMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC). INTFLAG.FAULTn flag rises on each local minimum detection.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bits 6:5 – BLANK[1:0] Recoverable Fault n Blanking Operation These bits, select the blanking start point for recoverable Fault n.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.8 Debug control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x1E 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 FDDBD DBGRUN R/W R/W 0 0 Bit 2 – FDDBD Fault Detection on Debug Break Detection This bit is not affected by software Reset and should not be changed by software while the TCC is enabled. By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bits 12, 13 – TCINV Timer/Counter Event x Invert Enable This bit inverts the event x input. Value Description 0 Input event source x is not inverted. 1 Input event source x is inverted. Bit 10 – CNTEO Timer/Counter Event Output Enable This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of counter cycle depending of CNTSEL[1:0] settings.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bits 2:0 – EVACT0[2:0] Timer/Counter Event Input 0 Action These bits define the action the TCC will perform on TCE0 event input 0. Value Name Description 0x0 OFF Event action disabled. 0x1 RETRIGGER Start, restart or re-trigger TC on event 0x2 COUNTEV Count on event.
PAGE 1860
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.10 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x24 0x00000000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
PAGE 1861
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Value 0 1 Description The Non-Recoverable Fault x interrupt is disabled. The Non-Recoverable Fault x interrupt is enabled. Bit 13 – FAULTB Recoverable Fault B Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable Fault B interrupt. Value Description 0 The Recoverable Fault B interrupt is disabled.
PAGE 1862
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Writing a '1' to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt. Value Description 0 The Counter interrupt is disabled. 1 The Counter interrupt is enabled. Bit 1 – TRG Retrigger Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt.
PAGE 1863
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.11 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x28 0x00000000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 1864
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Value 0 1 Description The Non-Recoverable Fault x interrupt is disabled. The Non-Recoverable Fault x interrupt is enabled. Bit 13 – FAULTB Recoverable Fault B Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable Fault B interrupt. Value Description 0 The Recoverable Fault B interrupt is disabled.
PAGE 1865
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Value 0 1 Description The Counter interrupt is disabled. The Counter interrupt is enabled. Bit 1 – TRG Retrigger Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt. Value Description 0 The Retrigger interrupt is disabled. 1 The Retrigger interrupt is enabled.
PAGE 1866
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Recoverable Fault B interrupt flag. Bit 12 – FAULTA Recoverable Fault A Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
PAGE 1868
SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bit 13 – FAULTB Recoverable Fault B State This bit is set by hardware as soon as recoverable Fault B condition occurs. This bit can be clear by hardware when Fault B action is resumed, or by writing a '1' to this bit when the corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.HALT=SW), clearing this bit will release the timer/counter.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bit 0 – STOP Stop This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One-Shot operation mode is enabled (CTRLBSET.ONESHOT=1). This bit is clear on the next incoming counter increment or decrement. Value Description 0 Counter is running. 1 Counter is stopped. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.14 Counter Value Name: Offset: Reset: Property: COUNT 0x34 0x00000000 PAC Write-Protection, Write-Synchronized, Read-Synchronized Note: Prior to any read access, this register must be synchronized by user by writing the according TCC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Bit 7 – CIPEREN Circular Period Enable Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back into the PERB register on UPDATE condition. Bits 5:4 – RAMP[1:0] Ramp Operation These bits select Ramp operation (RAMP). These bits are not synchronized.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE - 0x1 - DITH4 3:0 0x2 - DITH5 4:0 0x3 - DITH6 5:0 (depicted) © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.18 Compare/Capture Channel x Name: Offset: Reset: Property: CC 0x44 + n*0x04 [n=0..5] 0x00000000 Write-Synchronized, Read-Synchronized The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the mode of operation. For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Note: 1. When the TCC is configured as a 16-bit timer/counter, the excess bits are read as zero. 2. This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION): CTRLA.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE - 0x1 - DITH4 3:0 0x2 - DITH5 4:0 0x3 - DITH6 5:0 (depicted) © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications 49.8.21 Channel x Compare/Capture Buffer Value Name: Offset: Reset: Property: CCBUF 0x70 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet TCC – Timer/Counter for Control Applications Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE - 0x1 - DITH4 3:0 0x2 - DITH5 4:0 0x3 - DITH6 5:0 (depicted) © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PTC - Peripheral Touch Controller 50. 50.1 PTC - Peripheral Touch Controller Overview The Peripheral Touch Controller (PTC) acquires signals in order to detect a touch on the capacitive sensors. The external capacitive touch sensor is typically formed on a PCB, and the sensor electrodes are connected to the analog front end of the PTC through the I/O pins in the device. The PTC supports both self and mutual capacitance sensors.
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SAM D5x/E5x Family Data Sheet PTC - Peripheral Touch Controller 50.3 Block Diagram Figure 50-1. PTC Block Diagram Mutual Capacitance Input Control Compensation Circuit Y0 RS Y1 Charge Integrator Ym IRQ ADC System 10 Result CX0Y0 X0 X Line Driver X1 C XnYm Xn Figure 50-2. PTC Block Diagram Self Capacitance Input Control Compensation Circuit Y0 Y1 CY0 RS Charge Integrator Ym IRQ ADC System 10 Result CYm X Line Driver 50.4 Signal Description Table 50-1.
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SAM D5x/E5x Family Data Sheet PTC - Peripheral Touch Controller Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 6. I/O Multiplexing and Considerations 50.5 System Dependencies In order to use this peripheral, configure the other components of the system as described in the following sections. 50.5.
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SAM D5x/E5x Family Data Sheet PTC - Peripheral Touch Controller Figure 50-4. Self-Capacitance Sensor Arrangement MCU Sensor Capacitance Cy Y0 Cy0 Y1 Cy1 PTC Module Ym Cym For more information about designing the touch sensor, refer to Buttons, Sliders and Wheels Touch Sensor Design Guide. 50.5.2 Analog-Digital Converter (ADC) The PTC is using the ADC for signal conversion and acquisition. The ADC must be enabled and configured appropriately to allow correct behavior of the PTC. Related Links 45.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51. I2S - Inter-IC Sound Controller 51.1 Overview The Inter-IC Sound Controller (I2S) provides bidirectional, synchronous and digital audio link with external audio devices. This controller is compliant with the Inter-IC Sound (I2S) bus specification. It supports TDM interface with external multi-slot audio codecs. It also supports PDM interface with external MEMS microphones.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller • Master, slave, and controller modes: – Master: Data received/transmitted based on internally-generated clocks.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller ...........continued Pin Name Pin Description Type SDO Serial Data Output for Transmit Serializer Output SDI Serial Data Input for Receive Serializer Input Note: One signal can be mapped on several pins. Related Links 6. I/O Multiplexing and Considerations 51.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 51.5.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 22. DMAC – Direct Memory Access Controller 51.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using I2S interrupts requires the interrupt controller to be configured first. Related Links 10.2 Nested Vector Interrupt Controller 51.5.6 Events Not applicable. 51.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will continue normal operation.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Figure 51-2. Data Format: Frames, Slot, Bits and Clocks I2S supports multiple data formats such as: • 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format • 16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce data transfers In mono format, Transmit mode, data written to the left channel is duplicated to the right output channel.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller In TDM format, number slots can be configured up to 8 slots. If 4 slots are configured, each frame consists of 4 data words. In PDM format, continuous 1-bit data samples are available on the SDI line for each SCKn rising and SCKn falling edge as in case of a MEMS microphone with PDM interface. 1-channel burst transfer with non-periodic Frame Sync mode is useful typically for passing control nonauto data as in case of DSP.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Once the configuration has been written, the I2S Clock Units and Serializers can be enabled by writing a '1' to the CKENn, TXEN, and/or RXEN bits and to the ENABLE bit in the Control register (CTRLA). The Clock Unit n can be enabled alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn pins. The Clock Units must be enabled if Serializers are enabled.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller • I2S RX 1, • I2S TX 0, and • I2S TX 1. For further reference, these are called I2S_DMAC_ID_RX_m and I2S_DMAC_ID_TX_m triggers (m=0..1). By using these trigger sources, one DMA data transfer will be executed whenever the Receive Ready or Transmit Ready status bits are set. 51.6.2.1 Master Clock, Serial Clock, and Frame Sync Generation The generation of clocks in the I2S is described in the next figure. Figure 51-4. I2S Clocks Generation 51.6.2.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.6.2.1.2 Master Mode and Controller Mode In Master Mode, the Master Clock (MCKn), the Serial Clock (SCKn), and the Frame Sync Clock (FSn) are generated by the I2S controller. The user can configure the Master Clock, Serial Clock, and Word Select Frame Sync signal (Word Select in I2S mode and Frame Sync in TDM mode) using the Clock Unit n Control register (CLKCTRLn).
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller �MCKn = 8 ⋅ SLOTSIZE+1 ⋅ NBSLOTS+1 ⋅ MCKDIV+1 MCKOUTDIV+1 If a Master Clock output is not required, the GCLK_I2S generic clock can be configured as SCKn by writing a '0'to CLKCTRLn.MCKDIV. Alternatively, if the frequency of the generic clock is a multiple of the required SCKn frequency, the MCKn-to-SCKn divider can be used with the ratio defined by writing the CLKCTRLn.MCKDIV field.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Figure 51-5. I2S Reception and Transmission Sequence Bit Serial Clock SCKn Word Select FSn Data SDO/SDI MSB LSB MSB Right Channel Left Channel Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The Word Select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel. In I2S format, typical configurations are described below.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller By configuring RXCTRL and/or TXCTRL, data bits can be left-adjusted or right-adjusted in the slot. It can also configure the data transmission/reception with either the MSB or the LSB transmitted/received first and starting the transmission/reception either at the transition of the FSn pin or one clock period after. Figure 51-6.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller To configure PDM2 mode, set SLOTSIZE = 0x01 (16-bits), NBSLOTS = 0x00 (1 slots) and RXCTRL.DATASIZE = 0x00 (32-bit). 51.6.7 Data Formatting Unit To allow more flexibility, data words received by the Receive Serializer will be formatted by the Receive Formatting Unit before being stored into the Data Holding register (DATAm).
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.6.8.2 Interrupts The I2S has the following interrupt sources: • Receive Ready (RXRDYm): This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. • Receive Overrun (RXORm): This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. • Transmit Ready (TXRDYm): This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller • Clock Unit x Enable bits in the Control A register (CTRLA.CKENx). SYNCBUSY.CKENx is set to '1' while synchronization is in progress. • Serializer Enable bits in the Control A register (CTRLA.TXEN and CTRLA.RXEN). SYNCBUSY.TXEN/RXEN is set to '1' while synchronization is in progress. The following registers require synchronization when read or written: • Transmit Data register (TXDATA) is Write-Synchronized. SYNCBUSY.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Figure 51-8. Time Slot Application Block Diagram MCKn SCKn I2S FSn SDO SDI Master Clock Serial Clock EXTERNAL AUDIO CODEC for First Time Slot Frame Sync Serial Data Out Serial Data In EXTERNAL AUDIO CODEC for Second Time Slot Serial Clock First Time Slot Frame Sync Second Time Slot Dstart Dend Serial Data Out Serial Data In Figure 51-9.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Figure 51-10. PDM Microphones Application Block Diagram MCKn SCKn 64 fs Serial Clock EXTERNAL PDM MICROPHONE for Left Channel 2 IS FSn SDI Serial Data In L/RSEL VDD EXTERNAL PDM MICROPHONE for Right Channel L/RSEL GND Serial Clock Serial Data In © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.8 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 RXEN TXEN CKEN1 CKEN0 ENABLE FSOUTINV FSINV SWRST 0x01 ...
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller ...........continued Offset 0x30 0x34 51.9 Name TXDATA RXDATA Bit Pos. 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection 6 Access Reset 5 4 3 2 1 0 RXEN TXEN CKEN1 CKEN0 ENABLE SWRST R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 5 – RXEN Rx Serializer Enable Writing a '0' to this bit will disable the Rx Serializer. Writing a '1' to this bit will enable the Rx Serializer. Value Description 0 The Rx Serializer is disabled.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Value 1 Description The reset operation is ongoing. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.2 Clock Unit n Control Name: Offset: Reset: Property: Bit CLKCTRL 0x04 + n*0x04 [n=0..
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller MCKSEL Name Description 0x0 GCLK GCLK_I2S_n is used as Master Clock n source 0x1 MCKPIN MCKn input pin is used as Master Clock n source Bit 12 – SCKOUTINV Serial Clock Output Invert Value Description 0 The Serial Clock n is output without inversion. 1 The Serial Clock n is inverted before being output. Bit 11 – SCKSEL Serial Clock Select This field selects the source of the Serial Clock n.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller FSWIDTH[1:0] Name Description 0x0 SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x1 HALF Frame Sync Pulse is half a Frame wide 0x2 BIT Frame Sync Pulse is 1 Bit wide 0x3 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested Bits 4:2 – NBSLOTS[2:0] Number of Slots in Frame Each Frame for Clock Unit n is composed of (NBSLOTS + 1) Slots.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.3 Interrupt Enable Clear Name: Offset: Reset: Property: Bit 15 INTENCLR 0x0C 0x0000 PAC Write-Protection 14 Access Reset Bit 7 6 Access Reset 13 12 TXUR1 R/W 0 11 9 8 TXUR0 TXRDY1 TXRDY0 R/W R/W R/W 0 0 0 3 10 5 4 1 0 RXOR1 RXOR0 2 RXRDY1 RXRDY0 R/W R/W R/W R/W 0 0 0 0 Bits 12, 13 – TXURx Transmit Underrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.4 Interrupt Enable Set Name: Offset: Reset: Property: Bit 15 INTENSET 0x10 0x0000 PAC Write-Protection 14 Access Reset Bit 7 6 Access Reset 13 12 TXUR1 R/W 0 11 9 8 TXUR0 TXRDY1 TXRDY0 R/W R/W R/W 0 0 0 3 10 5 4 1 0 RXOR1 RXOR0 2 RXRDY1 RXRDY0 R/W R/W R/W R/W 0 0 0 0 Bits 12, 13 – TXURx Transmit Underrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.5 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 15 INTFLAG 0x14 0x0000 - 14 Access Reset Bit 7 6 Access Reset 13 12 TXUR1 R/W 0 11 9 8 TXUR0 TXRDY1 TXRDY0 R/W R/W R/W 0 0 0 3 10 5 4 1 0 RXOR1 RXOR0 2 RXRDY1 RXRDY0 R/W R/W R/W R/W 0 0 0 0 Bits 12, 13 – TXURx Transmit Underrun x [x=1..0] This flag is cleared by writing a '1' to it.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Bit 0 – SWRST Software Reset Synchronization Status This bit is cleared when the synchronization of the CTRLA.SWRST bit between the clock domains is complete. This bit is set when the synchronization of the CTRLA.SWRST bit between the clock domains is started. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Bit 15 – BITREV Data Formatting Bit Reverse This bit allows changing the order of data bits in the word in the Formatting Unit. BITREV Name Description 0x0 MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0x1 LSBIT Transfer Data Least Significant Bit (LSB) first Bits 14:13 – EXTEND[1:0] Data Formatting Bit Extension This field defines the bit value used to extend data samples in the Formatting Unit.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller SLOTADJ Name Description 0x0 RIGHT Data is right adjusted in slot 0x1 LEFT Data is left adjusted in slot Bit 4 – TXSAME Transmit Data when Underrun. TXSAME Name Description 0x0 ZERO Zero data transmitted in case of underrun 0x1 SAME Last data transmitted in case of underrun Bits 3:2 – TXDEFAULT[1:0] Line Default Line when Slot Disabled This field defines the default value driven on the SDn output pin during all disabled Slots.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller Bits 16, 17, 18, 19, 20, 21, 22, 23 – SLOTDISx Slot x Disabled for this Serializer [x=7..0] This field allows disabling some slots in each transmit frame: Value Description 0 Slot x is used for data transfer. 1 Slot x is not used for data transfer and will be output as specified in the TXDEFAULT field. Bit 15 – BITREV Data Formatting Bit Reverse This bit allows changing the order of data bits in the word in the Formatting Unit.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller ...........continued DATASIZE[2:0] Name Description 0x7 8C 8 bits compact stereo Bit 7 – SLOTADJ Data Slot Formatting Adjust This field defines left or right adjustment of data samples in the slot. SLOTADJ Name Description 0x0 RIGHT Data is right adjusted in slot 0x1 LEFT Data is left adjusted in slot Bit 5 – CLKSEL Clock Unit Selection.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.
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SAM D5x/E5x Family Data Sheet I2S - Inter-IC Sound Controller 51.9.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52. PCC - Parallel Capture Controller 52.1 Overview The Parallel Capture Controller can be used to interface an external system, such as a CMOS digital image sensor, ADC, or DSP, and capture its parallel data. 52.2 Features • • • • • 52.3 One clock, up to 14-bit parallel data and two Data Enable on I/O lines Data can be sampled every other time (e.g.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.5 Product Dependencies For the Parallel Capture Controller to function as intended, other interconnected modules of the system must be configured accordingly. 52.5.1 I/O Lines The PCC pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to assign the PCC pins to their peripheral functions. 52.5.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller The interrupt request line is connected to the interrupt controller. Using the interrupts requires the interrupt controller to be configured first. Refer to NVIC - Nested Interrupt Nested Vector Interrupt Controller for details. 52.5.6 Events Not applicable. 52.5.7 Debug Operation When the CPU is halted in debug mode, the PCC will not halt normal operation.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller Once enabled, the PCC samples the data at rising edge of the sensor clock, and resynchronizes it with the PCC clock domain. The input data bus size can be programmed using the Input Data Size bit field (MR.ISIZE). A re-initialization of the internal mechanism of the PCC can be automatically done by setting the CID register when a falling edge of the DEN1 or DEN2 is detected.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller Figure 52-3. PCC Waveforms (DSIZE=4_DATA, ALWYS = 0, HALFS = 0) MCLK CLK DATA[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x5645_3423 RHR.RDATA Figure 52-4. PCC Waveforms (ISIZE=10_BITS, DSIZE=2_DATA, ALWYS = 0, HALFS = 0, SCALE = 0) MCLK CLK DATA[9:0] 0x101 0x112 0x123 0x134 0x145 0x156 0x167 0x178 0x189 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x0134_0123 RHR.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller Figure 52-6. PCC Waveforms (DSIZE=4_DATA, ALWYS = 1, HALFS = 0) MCLK CLK DATA[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x3423_1201 RHR.RDATA 0x7867_5645 Figure 52-7. PCC Waveforms (ISIZE=10_BITS, DSIZE=2_DATA, ALWYS = 1, HALFS = 0, SCALE = 0) MCLK CLK DATA[9:0] 0x101 0x112 0x123 0x134 0x145 0x156 0x167 0x178 0x189 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x0112_0101 RHR.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller Figure 52-9. PCC Waveforms (DSIZE=4_DATA, ALWYS = 0, HALFS = 1, FRSTS = 0) MCLK CLK DATA[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x6745_2301 RHR.RDATA Figure 52-10. PCC Waveforms (ISIZE=10_BITS, DSIZE=2_DATA, ALWYS = 0, HALFS = 1, FRSTS = 0, SCALE = 0) MCLK CLK DATA[9:0] 0x101 0x112 0x123 0x134 0x145 0x156 0x167 0x178 0x189 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x0123_0101 RHR.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller Figure 52-12. PCC Waveforms (DSIZE=4_DATA, ALWYS = 0, HALFS = 1, FRSTS = 1) MCLK CLK DATA[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x7856_3412 RHR.RDATA Figure 52-13. PCC Waveforms (ISIZE=10_BITS, DSIZE=2_DATA, ALWYS = 0, HALFS = 1, FRSTS = 1, SCALE = 0) MCLK CLK DATA[9:0] 0x101 0x112 0x123 0x134 0x145 0x156 0x167 0x178 0x189 DEN1 DEN2 ISR.DRDY Read of ISR.DRDY 0x0134_0112 RHR.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.6.3 Programming Sequence 52.6.3.1 Without DMAC 1. 2. 3. 4. 5. 6. 7. 8. Write the Interrupt Enable and Interrupt Disable Registers (IER and IDR) in order to configure the PCC interrupt mask. Write the Mode Register (MR) fields ISIZE, SCALE, DSIZE, ALWYS, HALFS and FRSTS in order to configure the PCC. Do not enable the PCC in this write access. Write the PCC Enable bit in the Mode Register (MR.PCEN) to '1' in order to enable the PCC.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.7 Offset Register Summary Name Bit Pos.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 52.6.2 Register Access Protection. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.1 PCC Mode Register Name: Offset: Reset: Property: MR 0x00 0x00000000 - This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller Value 0 1 Description Only data with an even index are sampled. Only data with an odd index are sampled. Bit 10 – HALFS Half Sampling This function is independent from the ALWYS bit. Value Description 0 The Parallel Capture Controller samples all the data. 1 The Parallel Capture Controller samples the data only every other time.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.2 Interrupt Enable Register Name: Offset: Reset: Property: Bit IER 0x04 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Access Reset Bit Access Reset Bit Access Reset Bit 3 2 1 0 RXBUF ENDRX OVRE DRDY Access W W W W Reset 0 0 0 0 Bit 3 – RXBUF Reception Buffer Full Interrupt Enable.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.4 Interrupt Mask Register Name: Offset: Reset: Property: Bit IMR 0x0C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Access Reset Bit Access Reset Bit Access Reset Bit 3 2 1 0 RXBUFF ENDRX OVRE DRDY Access R R R R Reset 0 0 0 0 Bit 3 – RXBUFF Reception Buffer Full Interrupt Mask Value Description 1 The Reception Buffer Full interrupt is enabled.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller ...........continued ISIZE SCALE DSIZE Description 14_BITS 0 (OFF) 1_DATA RDATA[13:0] is useful 2_DATA RDATA[13:0] and RDATA[29:16] are useful 1_DATA RDATA[15:0] is useful 2_DATA RDATA[31:0] is useful 1 (ON) © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.
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SAM D5x/E5x Family Data Sheet PCC - Parallel Capture Controller 52.8.
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SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53. PDEC – Position Decoder 53.1 Overview The PDEC consists of a Quadrature / Hall decoder, following by a counter, with two compare channels. The counter can be split into two parts to report the angular position and the number of revolutions. If the quadrature decoder feature is not suitable for specific applications, the PDEC module can be used as an additional time base. 53.
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SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.3 Block Diagram Figure 53-1. Block Diagram sync Signal 0 PINVE PINEN EVINV QDEC_EV[0] EVEI 0 PDEC[0] CC1 MC1 (Interrupt or Event) CC0 MC0 (Interrupt or Event) COUNT OVF (Interrupt or Event) Control Logic Filter sync Signal 1 PINVE PINEN EVINV QDEC_EV[1] EVEI 0 PDEC[1] PDEC[2] 53.
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SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 18. PM – Power Manager 53.5.3 Clocks A generic clock (GCLK_PDEC) is required to clock the PDEC. This clock must be configured and enabled in the generic clock controller before using the PDEC. This generic clock is asynchronous to the bus clock (CLK_PDEC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Related Links 14. GCLK - Generic Clock Controller 13.3 Register Synchronization 53.
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SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Related Links 27. PAC - Peripheral Access Controller 53.5.9 Analog Connections Not applicable. 53.6 Functional Description 53.6.1 Principle of Operation The PDEC control logic can be driven by a set of three inputs signal coming from Event System channels or I/O input pins. These three inputs can be filtered prior to down-stream processing. The input polarity, phase definition and other factors are configurable.
PAGE 1950
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder The PDEC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The PDEC is disabled by writing a '0' to CTRLA.ENABLE. In QDEC or HALL operation modes, PDEC decoding is enabled writing a START command in the Control B Set register (CTRLBSET.CMD=START). The PDEC decoding is disabled writing a STOP command in the Control B Set register (CTRLBSET.CMD=STOP).
PAGE 1951
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Only the first two input signals can be swapped by writing to the SWAP bit in the Control A register (CTRLA.SWAP). Related Links 53.3 Block Diagram 53.6.2.5 Period Control The Channel Compare 0 register (CC0) can act as a period register (PER) by writing the PEREN bit in the Control A register (CTRLA.PEREN) to '1'.
PAGE 1952
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Figure 53-5. Position and Rotation Measurement PhaseA PhaseB Index DIR Event Angle OVF ERR CC0 (LSB) CC1 (LSB) Anglular Counter CC1 (MSB) Revolution Counter MC1 Event in Q4 and Q4S configuration, a valid index is detected when the three inputs (PhaseA, PhaseB and Index) are at low level. In Q2 and Q2S configuration, a valid index is detected when the two inputs (Count and Index) are at low level.
PAGE 1953
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Figure 53-6. Rotation Direction Change PhaseA PhaseB Anglular Counter DIR Event DIRCHG Interrupt VLC Event To avoid spurious interrupts when coding wheel is stopped, the direction change condition is reported as an interrupt, only on the second edge confirming the direction change. Velocity output event is generated on each QDEC transition except when the direction changes. 53.6.2.6.
PAGE 1954
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.6.2.6.4 Missing Pulse Detection and Auto-Correction The PDEC embeds circuitry to detect and correct errors that may result from contamination on optical disks or other sources producing quadrature phase signals. The auto-correction works in QDEC X4 mode only. A missing pulse on a phase signal is automatically detected, and the pulse count reported in the Angular part of COUNT is automatically corrected.
PAGE 1955
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder • The filter output value is checked to be a valid Hall value. If an invalid Hall code is reported, the Hall Error bit in Status register will be set (STATUS.HERR). • The MC0 Interrupt Flag bit is set (INTFLAG.MC0) if CC0[2:0] matches the filter output value. An optional compare match interrupt or Event output is generated on the same condition detection. • The window counter is checked to be between CC0[MSB] and CC1[MSB] value, and reset to 0 value.
PAGE 1956
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.6.3.3 Register Lock Update Prescaler (PRESC), FILTER, and CCx registers are buffered (PRESCBUF, FILTERBUF, CCBUFx registers, respectively). When a new value is written in a buffer register, the corresponding Buffer Valid bit is set in the Buffer Status register (STATUS.FILTERBUFV, STATUS.PRESCBUFV, STATUS.CCBUFVx).
PAGE 1957
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.6.4 Interrupts The PDEC has the following interrupt sources: • • • • • Overflow/Underflow: OVF Compare Channels: COMPx Error: ERR Velocity: VLC. This interrupt is available only in QDEC and HALL operation modes. Direction: DIR. This interrupt is available only in QDEC and HALL operation modes. Each interrupt source has an interrupt flag associated with it.
PAGE 1958
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder • • • • • • Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET) Status register (STATUS) Prescaler and Prescaler Buffer registers (PRESC and PRESCBUF) Compare Value x and Compare Value x Buffer registers (CCx and CCBUFx) Filter Value and Filter Buffer Value registers (FILTER and FILTERBUF) Counter Value register (COUNT) Required write synchronization is denoted by the "Write-Synchronized" property in the register description.
PAGE 1959
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.7 Offset Register Summary Name Bit Pos.
PAGE 1960
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder ...........continued Offset Name Bit Pos. 0x28 ... Reserved 0x2F 0x30 CCBUF0 7:0 CCBUF[7:0] 15:8 CCBUF[15:8] 23:16 31:24 0x34 CCBUF1 7:0 CCBUF[7:0] 15:8 CCBUF[15:8] 23:16 31:24 53.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
PAGE 1961
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.
PAGE 1962
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder ...........continued ANGULAR[2:0] Angular counter Revolution counter 0x2 COUNTER[0:10] COUNTER[11:15] 0x3 COUNTER[0:11] COUNTER[12:15] 0x4 COUNTER[0:12] COUNTER[13:15] 0x5 COUNTER[0:13] COUNTER[14:15] 0x6 COUNTER[0:14] COUNTER[15] 0x7 COUNTER[0:15] no revolution counter Bits 20, 21, 22 – PINVEN IO Pin x Invert Enable When this bit is written to '1', the corresponding input pin active level is inverted.
PAGE 1963
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Value 0 1 Description Auto Lock is disabled. Auto Lock is enabled. Bits 10:8 – CONF[2:0] PDEC Configuration These bits define the PDEC configuration. Outside of QDEC mode, these bits have no effect. These bits are not synchronized.
PAGE 1964
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Value 1 Description A Reset operation is ongoing. © 2019 Microchip Technology Inc.
PAGE 1965
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.2 Control B Clear Name: Offset: Reset: Property: CTRLBCLR 0x04 0x00 PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.
PAGE 1966
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.3 Control B Set Name: Offset: Reset: Property: CTRLBSET 0x05 0x00 PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear (CTRLBCLR) register.
PAGE 1967
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.
PAGE 1968
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Value 1 Description Overflow/Underflow event is enabled and will be generated for every counter overflow/ underflow. Bits 7:5 – EVEI[2:0] Event Input Enable This bit is used to enable asynchronous input event to the counter. Value Description 0 Incoming events are disabled. 1 Incoming events are enabled. Bits 4:2 – EVINV[2:0] Inverted Event Input Enable This bit inverts the asynchronous input event to the counter.
PAGE 1969
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.5 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x08 0x00 PAC Write-Protection This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
PAGE 1970
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Writing a '1' to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. © 2019 Microchip Technology Inc.
PAGE 1971
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.6 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x09 0x00 PAC Write-Protection This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 1972
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enable the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. © 2019 Microchip Technology Inc.
PAGE 1973
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.
PAGE 1974
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.
PAGE 1975
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder The flag is cleared by writing a '1' to this bit location. Outside of HALL mode, this bits is always read '0'. Bit 4 – WINERR Window Error Flag This flag is set when the counter is outside the window monitor. The flag is cleared by writing a '1' to this bit location. Outside of HALL mode, this bits is always read '0'. Bit 2 – MPERR Missing Pulse Error flag This flag is set when a missing pulse error condition is detected.
PAGE 1976
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.9 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0F 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access RW Reset 0 Bit 0 – DBGRUN Debug Run Mode This bit is not affected by software reset and should not be changed by software while the PDEC module is enabled. Value Description 0 The PDEC module is halted when the device is halted in debug mode.
PAGE 1977
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.
PAGE 1978
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder Bit 2 – CTRLB Control B Synchronization Busy This bit is cleared when the synchronization of Control B register between the clock domains is complete. This bit is set when the synchronization of Control B register between clock domains is started. Bit 1 – ENABLE Enable Synchronization Busy This bit is cleared when the synchronization of Enable register bit between the clock domains is complete.
PAGE 1979
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.11 Prescaler Value Name: Offset: Reset: Property: Bit 7 PRESC 0x14 0x00 Write-Synchronized 6 5 4 3 2 1 0 RW RW 0 RW RW 0 0 0 PRESC[3:0] Access Reset Bits 3:0 – PRESC[3:0] Prescaler Value These bits select the GCLK prescaler factor. Value Name 0 DIV1 1 DIV2 2 DIV4 3 DIV8 4 DIV16 5 DIV32 6 DIV64 7 DIV128 8 DIV256 9 DIV512 10 DIV1024 © 2019 Microchip Technology Inc.
PAGE 1980
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.12 Filter Value Name: Offset: Reset: Property: Bit FILTER 0x15 0x00 Write-Synchronized 7 6 5 4 3 2 1 0 RW RW RW RW 0 0 0 RW RW RW RW 0 0 0 0 0 FILTER[7:0] Access Reset Bits 7:0 – FILTER[7:0] Filter Value These bits select the PDEC inputs filter length. These bits have no effect when COUNTER operation mode is selected. © 2019 Microchip Technology Inc.
PAGE 1981
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.13 Prescaler Buffer Value Name: Offset: Reset: Property: Bit 7 PRESCBUF 0x18 0x00 Write-Synchronized 6 5 4 3 2 1 0 RW RW RW RW 0 0 0 0 PRESCBUF[3:0] Access Reset Bits 3:0 – PRESCBUF[3:0] Prescaler Buffer Value These bits hold the value of the prescaler buffer register. The value is copied in the corresponding PRESC register on UPDATE condition.
PAGE 1982
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.14 Filter Buffer Value Name: Offset: Reset: Property: Bit FILTERBUF 0x19 0x00 Write-Synchronized 7 6 5 4 RW RW RW RW 0 0 0 0 3 2 1 0 RW RW RW RW 0 0 0 0 FILTERBUF[7:0] Access Reset Bits 7:0 – FILTERBUF[7:0] Filter Buffer Value These bits hold the value of the filter buffer register. The value is copied in the corresponding FILTER register on UPDATE condition.
PAGE 1983
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.
PAGE 1984
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.16 Channel x Compare Value Name: Offset: Reset: Property: Bit CCx 0x20 + x*0x04 [x=0..
PAGE 1985
SAM D5x/E5x Family Data Sheet PDEC – Position Decoder 53.8.17 Channel x Compare Buffer Value Name: Offset: Reset: Property: Bit CCBUFx 0x30 + x*0x04 [x=0..
PAGE 1986
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C 54. Electrical Characteristics at 85°C 54.1 Disclaimer All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. 54.2 Absolute Maximum Ratings Stresses beyond those listed in the table below may cause permanent damage to the device.
PAGE 1987
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Description Min. Typ. Max. Units TA Temperature range -40 25 85 °C TJ Junction temperature - - 105 °C VBAT Battery Supply Voltage 1.71(1) 3.3 3.63 V Note: 1. With BOD33 disabled. 2. The same voltage must be applied to VDDIO and VDDANA. VDDIOB should be lower or equal to VDDIO / VDDANA. The common voltage is referred to as VDD in the data sheet. 3.
PAGE 1988
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Note: 1. VIL source < (VSS - 0.6). Characterized but not tested. 2. VIH source > (VDDIO + 0.6) for non-5V tolerant pins only. 3. Digital 5V tolerant pins do not have an internal high side diode to VDDIO, and therefore, cannot tolerate any “positive” input injection current. 4. Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDDIO + 0.6) or VIL source < (GND - 0.6)). 5.
PAGE 1989
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-6. Power Supply Current Requirement Symbol Conditions Current Units Max Iinput Power-up Maximum Current 7 mA Note: Iinput is the minimum requirement for the power supply connected to the device. 54.6 Maximum Clock Frequencies Table 54-7.
PAGE 1990
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Description Max. Units fGCLK_CANx, x = {0, 1} CANx input clock frequency 100 MHz fGCLK_USB USB input clock frequency 60 MHz fGCLK_I2S I2S input clock frequency 100 MHz fGCLK_SDHCx_SLOW, x = {0, 1} Common SDHCx slow input clock frequency 12 MHz fGCLK_SDHCx_CORE, x = {0, 1} SDHCx input clock frequency 150 MHz fGCLK_TCCx, x = {0, ...
PAGE 1991
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-9. Active Current Consumption - Active Mode Mode Conditions Regulator Clock FDPLL 120 MHz LDO DFLL 48 MHz XOSC 32 MHz Active COREMARK(1) FDPLL 120 MHz BUCK DFLL 48 MHz XOSC 32 MHz FDPLL 120 MHz LDO DFLL 48 MHz XOSC 32 MHz Idle N/A FDPLL 120 MHz BUCK DFLL 48 MHz XOSC 32 MHz VDD TA Typ Max. 1.8V 136 162 3.3V 137 164 1.8V 136 199 3.3V 136 199 1.8V 146 243 3.3V 149 245 1.8V 103 127 3.
PAGE 1992
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-10. Standby Mode Current Consumption Mode Regulator VDD(1) Mode Conditions Fast wake-up disabled (PM.STDBYCFG.FASTWKUP = 0x0), no peripheral running No System RAM retained (PM.STDBYCFG.RAMCFG = 0x2). 8 KB backup RAM retained Fast wake-up enabled (PM.STDBYCFG.FASTWKUP = 0x3), no peripheral running No System RAM retained (PM.STDBYCFG.RAMCFG = 0x2). 8 KB backup RAM retained LDO BUCK LDO BUCK Standby Fast wake-up disabled (PM.
PAGE 1993
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-11. Hibernate Mode Current Consumption Mode Regulator VDD(1) Mode Conditions No peripheral running No System RAM retained (PM.HIBCFG.RAMCFG = 0x2) No backup RAM retained (PM.HIBCFG.BRAMCFG = 0x2) RTC is running on XOSC32K No System RAM retained (PM.HIBCFG.RAMCFG = 0x2) No backup RAM retained (PM.HIBCFG.BRAMCFG = 0x2) RTC is running on XOSC32K No System RAM retained (PM.HIBCFG.RAMCFG = 0x2) 4 KB backup RAM retained (PM.HIBCFG.
PAGE 1994
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-12. Backup and Off Mode Current Consumption Mode VDD(1) Conditions TA Typ. Max. Units Powered by VDDIO, no RTC running VDDIO+VDDANA 1.8V consumption No backup RAM retained (PM.BKUPCFG.BRAMCFG 3.3V = 0x2) Backup 2.1 41.7 2.5 42.5 Powered by VDDIO with RTC running on XOSC32K VDDIO +VDDANA consumption No backup RAM retained (PM.BKUPCFG.BRAMCFG = 0x2) 1.8V 2.7 42.6 3.3V 3.3 43.
PAGE 1995
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-13. Wake-Up Timing Sleep Mode Conditions Typ Unit IDLE 230 ns STANDBY 54.9 STDBYCFG.FASTWKUP = 0 110 µs STDBYCFG.FASTWKUP = 1 Fast Wakeup is enabled on NVM. 92 µs STDBYCFG.FASTWKUP = 2 Fast Wakeup is enabled on the main voltage regulator. 25 µs STDBYCFG.FASTWKUP = 3 Fast Wakeup is enabled on both NVM and MAINVREG.
PAGE 1996
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-16. I/O Pins Dynamic Characteristics (see Notes 1, 2, and 3) Symbol Parameter Conditions Backup Pins in Backup Mode Backup and Normal Pins Backup and Normal Pins DRVSTR=0 DRVSTR=1 tRISE Maximum Rise Time CLOAD = 30 pF 4 0.04 0.01 tFALL Maximum Fall Time 4 0.04 0.01 CLOAD = 30 pF Units µs The pins with I2C alternative mode available are compliant with I2C specification.
PAGE 1997
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Parameter LEXT External inductance Conditions Min. Typ. Max. Units - 10 - µH RSERIES_LEXT ESR of LEXT - - - 0.36 Ω ISAT_LEXT - 500 - - mA Saturation current Note: 1. These values are based on simulation. They are not covered by production test limits or characterization. 2. It is recommended to use ceramic X7R capacitor with low-series resistance.
PAGE 1998
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C VDD Figure 54-1. POR Operating Principle VPOT+ VPOT- Reset Time Note: The shaded area indicates that the device is in a Reset state. 54.10.3 Brown-Out Detectors (BOD) Characteristics Figure 54-3. BOD33 Hysteresis OFF VCC VBOD RESET Figure 54-4. BOD33 Hysteresis ON VCC VBOD+ VBOD- RESET © 2019 Microchip Technology Inc.
PAGE 1999
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-21. BOD33 Characteristics on VDD and VBAT Monitoring in Normal Mode (During Powerup Phase and Active Mode) Symbol Parameters VBOD or VBOD- (1) BOD33 threshold level Hysteresis OFF or BOD33 threshold level Hysteresis ON VBOD+ (2) BOD33 threshold level Hysteresis ON at power voltage rising Level_Step DC threshold step Tstart Startup time (6) Conditions (see Notes 3, 4) Min Typ Max Unit LEVEL[7:0] = 0x00 (min) 1.463 1.
PAGE 2000
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-22. BOD33 Characteristics on VDD and VBAT Monitoring in Low-Power Mode (During Standby/Backup/Hibernate Modes) Symbol Parameters VBOD or VBOD- (1) BOD33 threshold level Hysteresis OFF or BOD33 threshold level Hysteresis ON VBOD+ (2) BOD33 threshold level Hysteresis ON at power voltage rising Level_Step DC threshold step Tstart Startup time (6) Conditions (see Notes 3, 4) Min Typ Max Unit LEVEL[7:0] = 0x00 (min) 1.
PAGE 2001
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-23. BOD33 Power Consumption Symbol CPU Mode Conditions TA IDD VCC = 1.8V Max 85°C Typ 25°C 8.52 Active / Idle Typ. VCC = 3.3V Max Units 12.07 µA 10.10 14.28 Standby with BOD continuous normal VCC = 1.8V mode VCC = 3.3V 4.71 6.34 6.01 8.06 Standby with BOD continuous low power mode or Hibernate mode VCC = 1.8V 0.15 0.22 VCC = 3.3V 0.21 0.30 54.10.4 Analog-to-Digital Converter (ADC) Characteristics Table 54-24.
PAGE 2002
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Parameters Conditions TS Sampling time SAMPCTRL.OFFCOMP=1 REFCTRL.REFCOMP=1 CTRLC.R2R =1 Sampling time with DAC as input Min. Typ. Max. 4 SAMPCTRL.OFFCOMP=0(3) REFCTRL.REFCOMP=0 CTRLC.R2R=0 1 SAMPCTRL.OFFCOMP=1 REFCTRL.REFCOMP=1 (4) - Unit Cycles 65 ns CTRLC.R2R=1 SAMPCTRL.OFFCOMP=0 (3) REFCTRL.REFCOMP=0 CTRLC.R2R=0 Sampling time with Temp Sensor or Bandgap as input SAMPCTRL.OFFCOMP=1 REFCTRL.
PAGE 2003
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-5. ADC Analog Input AINx The minimum sampling time tsamplehold for a given Rsource can be found using a general formula: �samplehold ≥ �sample + �source × �sample × � + 2 × ln 2 For 12-bit accuracy, this turns into: �samplehold ≥ �sample + �source × �sample × 9.7 1 where �samplehold ≥ . 2 × �ADC Table 54-25.
PAGE 2004
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Parameter SFDR Spurious Free Dynamic Range SINAD Signal to Noise and Distortion ratio SNR Signal to Noise ratio THD Total Harmonic Distortion Nrms Noise RMS Conditions Fs = 1Msps Fin = 14kHz (2) constant input voltage Measurement Min Typ Max 76.6 79.6 83.5 65.3 67.2 68.9 64.7 66.5 68.2 -91.6 -82.9 -78.6 Vddana=3.0V ExtVref=2.0V 0.2 0.4 2.4 Vddana=3.0V Vref=Vddana 0.15 0.25 2.
PAGE 2005
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Note: 1. These values are based on characterization. These values are not covered by test limits in production. 2. All values expressed in decibel refer to the full scale input and are tested with an input signal 0.35dB below full scale; THD measured on the first seven harmonics of the input signal. Table 54-27.
PAGE 2006
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Note: 1. These values are based on simulation. They are not covered by production test limits or characterization. Table 54-29. Differential Mode (1) Symbol Parameters Conditions INL Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F i12clk = 12 MHz, VDDANA = 3.0V, External Ref. = 2.0V, CLOAD = 50 pF - ±2.4 ±3.4 i12clk = 12 MHz, VDDANA = 3.0V, Internal Ref, CLOAD = 50 pF - ±3.2 ±4.
PAGE 2007
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Parameters Conditions Offerr External Reference voltage - ±7 ±21 1.0V Internal Reference voltage - ±2 ±16 Offset Error ENOB Effective Number of Bits SNR THD Min. Typ. Max. Fs = 1 Ms/s - External Ref - CCTRL = 0x2 9.1 Unit mV 10.3 10.7 Bits Signal to Noise Ratio 63.5 68.6 72.6 dB Total Harmonic Distortion -79.1 -72.8 -61.0 dB Note: 1. These values are based on characterization.
PAGE 2008
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Note: 1. These values are based on simulation. They are not covered by production test limits or characterization. 2. Hysteresis disabled. Table 54-33. Power Consumption Symbol Parameters Conditions Ta IDDANA COMPCTRLn.SPEED=0x3, VDDANA=3.3V Max.85°C 59 Typ.25°C 93 11 21 Current consumption for One AC enabled, Hysteresis disabled voltage scaler disabled Typ. Max. Unit Current consumption Voltage Scaler only VDDANA=3.3V µA 54.10.
PAGE 2009
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C 54.11 PTC Characteristics Table 54-35. Sensor Load Capacitance Symbol Mode PTC channel Max Sensor Load (1) Units Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 54 Y9 Y10 Y11 Y12 Y13 Y14 Cload Self-capacitance Y15 Y16 51 pF Y17 Y18 Y19 54 Y20 Y21 51 Y22 Y23 Y24 Y25 Y26 Y27 54 Y28 Y29 Y30 Y31 Mutual-capacitance All 31 Note: 1. Capacitance load that the PTC circuitry can compensate for each channel. © 2019 Microchip Technology Inc.
PAGE 2010
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-36. Analog Gain Settings (1) (2) Symbol Gain Setting Average GAIN_1 1 GAIN_2 2.0 GAIN_4 4.2 GAIN_8 9.1 GAIN_16 15.4 GAIN_32 - Note: 1. Analog Gain is a parameter of the QTouch Library. Refer to the “QTouch Library Peripheral Touch Controller User Guide” for additional information. 2. The GAIN_16 and GAIN_32 settings are not recommended; otherwise, the PTC measurements might become unstable.
PAGE 2011
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-37. Power Consumption (1) Symbol PTC scan rate (msec) Parameters Oversamples 10 50 IDD 137 1164 16 146 1179 4 77 1094 79 1100 68 1086 16 69 1089 4 64 1085 16 65 1087 Max 85°C Typ 25°C 4 100 200 Typ. Max Units 4 16 Current Consumption Ta µA Note: 1. These values are based on characterization. 54.12 NVM Characteristics Table 54-38.
PAGE 2012
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Note: 1. These are based on simulation. They are not covered by production test limits or characterization. Table 54-41. Flash Endurance and Data Retention Symbol Parameter Conditions Min. Typ. Units RetNVM10k Retention after up to 10k At TA = 85°C 20 - Years CycNVM Cycling Endurance(1) At TA = 85°C 10K - Cycles Note: 1. An endurance cycle is a write-and-erase operation. Table 54-42.
PAGE 2013
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-6. Oscillator Connection DEVICE XIN Crystal CLEXT LM RM CSHUNT CM XOUT CLEXT The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the Table. The exact value of CL can be found in the crystal datasheet.
PAGE 2014
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Note: 1. To ensure that the crystal is not overdriven, the automatic loop control is recommended to be turned ON (ENALC = 1). Table 54-45. Power Consumption Symbol Parameters Conditions Ta IDD F = 8 MHz - CL = 20 pF - IMULT = 0x3, ENALC = OFF Max. 85°C, Typ. 0.43 1.02 25°C Current Consumption Typ. Max. Units ENALC = ON 0.16 0.66 F = 16 MHz - CL = 20 pF - IMULT = 0x5, ENALC = OFF 1.31 2.39 ENALC = ON 0.25 0.
PAGE 2015
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-7. Oscillator Crystal Connection DEVICE XIN32 Crystal CLEXT LM RM CSHUNT CM XOUT32 CLEXT The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal data sheet.
PAGE 2016
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-48. Power Consumption Symbol Parameter Condition s Ta Gain Mode Typ. Max. Units IDD Current VDD=3.0V consumptio n Max 85°C Typ 25°C Std. 1.5 2 µA High 1.9 3 54.13.3 Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics Table 54-49. Ultra-Low-Power Internal 32 kHz RC Oscillator Electrical Characteristics Symbol Parameter Calibration Conditions Min. Typ.
PAGE 2017
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-8. Average Frequency Versus Calibration Code Value, VDD = 3V 54.13.4 Digital Frequency Locked Loop (DFLL48M) Characteristics Table 54-50. DFLL48M Characteristics - Open Loop Mode (1) Symbol Parameter Conditions Min. Typ. Max. Units FOpenOUT Output frequency DFLLVAL after Reset LDO Regulator mode, [-40, 85]°C 45.8 48 49.3 MHz DFLLVAL after Reset LDO Regulator mode, [0, 60]°C 47.2 48 48.
PAGE 2018
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Parameter Conditions FCloseJitter Period Jitter fREF = XTAL, 32.768 kHz, 100 ppm Min. Typ. Max. Units - - 0.42 ns - 429 1145 µs DFLLMUL = 1464 TLock Lock time FREF = XTAL, 32.768 kHz, 100 ppm DFLLMUL = 1464 DFLLVAL after Reset DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 Note: 1. These values are based on simulation.
PAGE 2019
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Note: 1. These values are based on simulation. They are not covered by production test limits or characterization. 2. These FDPLL200M characteristics are applicable with LDO regulator and a direct reference (i.e., REFCLK is XOSC or XOSC32K, not GCLK). Table 54-54. Power Consumption Symbol Parameter Conditions TA Typ. Max. Units IDD Current Consumption Clk = 96 MHz, VDD = 3.3V Max. 85°C Typ. 25°C 0.9 1.3 mA 2 2.
PAGE 2020
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C 54.14.2 SERCOM in SPI Mode Timing Table 54-56. SPI Timing Characteristics and Requirements(1) Symbol Parameter Conditions Min. Typ. Max. Units tSCK(10) Master Reception 2*(tMIS +tSLAVE_OUT)(3) - - ns Master Transmission 2*(tMOV+tSLAVE_IN) - - SCK period (4) tSCKW SCK high/low width Master - 0.5*tSCK - tSCKR SCK rise time(2) Master - 0.25*tSCK - tSCKF SCK fall time(2) Master - 0.
PAGE 2021
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units tSSCK Slave Reception 2*(tSIS +tMASTER_OUT)(5) - - ns Slave Transmission 2*(tSOV +tMASTER_IN)(6) - - Slave SCK Period tSSCKW SCK high/low width Slave - 0.5*tSSCK tSSCKR SCK rise time(2) Slave - 0.25*tSSCK - tSSCKF SCK fall time(2) Slave - 0.25*tSSCK - tSIS MOSI setup to SCK Slave, VDD>2.70V 7.5 - - Slave, VDD>1.71V 8.
PAGE 2022
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C – Reception: tSCK = 2*(tMIS+tSLAVE_OUT) = 2*(18 + 8) = 52nS – Transmission: tSCK = 2*(tMOV+tSLAVE_IN) = 2*(9 + 20) = 58nS Figure 54-9. SPI Timing Requirements in Master Mode SS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOV tMOH tMOH MOSI (Data Output) MSB LSB Figure 54-10.
PAGE 2023
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-12. QSPI SDR Master Mode 1 QSCK QSPI3 QSPI4 QSPI6 QSPI7 QIOx_DIN QSPI5 QIOx_DOUT Figure 54-13. QSPI SDR Master Mode 2 QSCK QIOx_DIN QSPI8 QIOx_DOUT Figure 54-14. QSPI SDR Master Mode 3 QSCK QSPI9 QSPI10 QIOx_DIN QSPI11 QIOx_DOUT Figure 54-15. QSPI DDR Mode 0 READ © 2019 Microchip Technology Inc.
PAGE 2024
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-16. QSPI DDR Mode 0 WRITE Table 54-57. QSPI Timing Characteristics (see Note 1) Name Description Mode VDD = 1.8V VDD = 3.3V Units Min. Typ. Max. Min. Typ. Max. fSDR_m0_m2 QSPI SDR Frequency Master SDR Mode 0/2 - - 50.0 - - 75 fSDR_m1_m3 QSPI SDR Frequency Master SDR Mode 1/3 - - 50.0 - - 50 fDDR QSPI DDR Frequency Master mode - - 37.5 - - 66 tSDR_QSPI0 Input Setup Time Master SDR mode 0 3.86 - - 3.
PAGE 2025
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Name Description Mode VDD = 1.8V VDD = 3.3V Units Min. Typ. Max. Min. Typ. Max. tDDR_QSPI0f Input Setup Time Master DDR mode 0 fall edge 3.87 - - 3.85 - - tDDR_QSPI1f Input Hold Time Master DDR mode 0 fall edge 0.00 - - 0.19 - - tDDR_QSPI2f Data Out Valid Time Master DDR mode 0 fall edge - - 2.1 - - 2.03 tDDR_QSPI0r Input Setup Time Master DDR mode 0 rise edge 3.81 - - 3.
PAGE 2026
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C 54.14.4 GMAC Characteristics Timing Conditions Table 54-59. GMAC Load Capacitance on Data, Clock Pads Symbol Description Condition Min. Max. Units CL Load Capacitance VDD=3.3V 0 20 pF Timing Constraints The GMAC must be constrained so as to satisfy the timings of standards given the following two tables, in MAX corner. Table 54-60. Minimum and Maximum Access Time of GMAC Output Signals Symbol Parameter Min. Max.
PAGE 2027
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C MII Mode Table 54-61.
PAGE 2028
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-18. GMAC MII Mode Signals EMDC GMAC1 GMAC3 GMAC2 EMDIO GMAC4 GMAC5 GMAC6 GMAC7 ECOL ECRS ETXCK GMAC8 ETXER GMAC9 ETXEN GMAC10 ETX[3:0] ERXCK GMAC11 GMAC12 ERX[3:0] GMAC13 GMAC14 GMAC15 GMAC16 ERXER ERXDV © 2019 Microchip Technology Inc.
PAGE 2029
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C RMIII Mode Table 54-62. GMAC RMII Mode Timings Symbol Parameter Min. Max.
PAGE 2030
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C 54.14.5 I2S Characteristics Table 54-63. I2S Timing Characteristics and Requirements (see Note 1) Name Description Mode VDD = 1.8V VDD = 3.3V Units Min. Typ. Max. Min. Typ. Max. tM_MCKOR I2S MCK rise time(2) Master mode / Capacitive load CL = 20 pF - - 5.41 - - 2.68 ns tM_MCKOF I2S MCK fall time (2) Master mode / Capacitive load CL = 20 pF - - 5.84 - - 2.81 ns dM_MCKO I2S MCK duty cycle Master mode - 50.0 - - 50.
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SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C ...........continued Name Description Mode VDD = 1.8V VDD = 3.3V Units Min. Typ. Max. Min. Typ. Max. tS_SDIH Data input hold time tM_SDOV Slave mode -1.1 - - -1.0 - - ns Data output valid time Master transmitter - - 3.7 - - 3.0 ns tM_SDOH Data output hold time Master transmitter -0.5 - - -0.5 - - ns tS_SDOV Data output valid time Slave transmitter - - 16.4 - - 12.
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SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Figure 54-20. Master Mode: SCK, FX, and MCK are Output Figure 54-21. Slave Mode: SCK and FS are Input Figure 54-22. PDM2 Mode © 2019 Microchip Technology Inc.
PAGE 2033
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C 54.14.6 PCC Characteristics Speed requirements for all 8/10/12/14-bits are: • pclk: 48 MHz at 3.3V • pclk: 28 MHz at 1.8V APB clock minimum is 2 × N pclk Figure 54-23. PCC Signaling 54.15 USB Characteristics The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications.
PAGE 2034
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 85°C Table 54-64. GCLK_USB Clock Setup Recommendations Clock setup DFLL48M FDPLL USB Device USB Host Open loop No No Close loop, Ref. internal OSC source No No Close loop, Ref. external XOSC source Yes No Close loop, Ref. SOF (USB recovery mode)(1) Yes(2) N/A internal OSC (32K, 8M…) No No external OSC (<1MHz) Yes No external OSC (>1MHz) Yes(3) Yes Note: 1.
PAGE 2035
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C 55. Electrical Characteristics at 105°C The specifications for 105°C temperature devices are identical to those shown in 54. Electrical Characteristics at 85°C, with the exception of the parameters listed in this chapter. 55.1 General Operating Ratings (105°C) The device must operate within the ratings listed below in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 55-1.
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SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-3. Active Current Consumption - Active Mode Mode conditions Regulator Clock VDD TA FDPLL 120MHz LDO DFLL 48MHz XOSC 32MHz ACTIVE COREMARK (1) FDPLL 120MHz BUCK DFLL 48MHz XOSC 32MHz LDO DFLL 48MHz XOSC 32MHz IDLE NA FDPLL 120MHz BUCK 1.8 136 191 3.3 137 193 1.8 136 271 3.3 136 272 1.8 146 346 3.3 149 347 1.8 103 151 3.3 65 1.8 102 225 3.3 63 1.8 110 283 3.
PAGE 2037
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-4. Standby, Hibernate, Backup and OFF Mode Current Consumption Mode Conditions Regulator Mode fast wake-up disabled (PM.STDBYCFG.FASTWKUP=0x0), no peripheral running LDO No System RAM retained (PM.STDBYCFG.RAMCFG=0x2). 8KB backup RAM retained BUCK fast wake-up enabled (PM.STDBYCFG.FASTWKUP=0x3), no peripheral running LDO No System RAM retained (PM.STDBYCFG.RAMCFG=0x2).
PAGE 2038
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C ...........continued Mode Conditions Typ. Max. 1.8V 6 168 3.3V 6 170 1.8V 3 111 3.3V 3 111 1.8V 6 169 3.3V 7 172 1.8V 3 113 3.3V 3 112 1.8V 7 193 3.3V 8 196 1.8V 3 129 4 128 7 217 3.3V 8 219 1.8V 4 144 3.3V 4 143 1.8V 9 350 3.3V 10 352 1.8V 5 233 3.3V 4 228 1.8V 16 873 3.3V 17 874 1.8V 9 580 3.3V 7 431 powered by VDDIO, no RTC running VDDIO+VDDANA consumption 1.8V 2.
PAGE 2039
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C 55.4 Analog Characteristics (105°C) 55.4.1 Power-On Reset (POR) Characteristics (105°C) Table 55-5. POR Characteristics Symbol Parameters Min. Typ. Max. Unit VPOT+ Voltage threshold Level on VDDIO rising 1.52 1.58 1.65 V VPOT- Voltage threshold Level on VDDIO falling 0.97 1.26 1.36 V VDD Figure 55-1. POR Operating Principle VPOT+ VPOT- Reset Time Note: The shaded area indicates that the device is in a Reset state.
PAGE 2040
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-6. BOD33 Characteristics on VDD and VBAT Monitoring in Normal Mode (During Power-up Phase and Active Mode) Symbol Parameters VBOD or VBOD- (1) BOD33 threshold level Hysteresis OFF or BOD33 threshold level Hysteresis ON VBOD+ (2) BOD33 threshold level Hysteresis ON at power voltage rising Conditions (3, 4) Min Typ Max Unit LEVEL[7:0] = 0x00 (min) 1.453 1.509 1.554 V LEVEL[7:0] = 0x19 (recommended value) 1.598 1.
PAGE 2041
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-7. BOD33 Characteristics on VDD and VBAT Monitoring in Low-Power Mode (During Standby/Backup/Hibernate Modes) Symbol Parameters Conditions (see Notes 3, 4) Min Typ Max Unit VBOD or VBOD( see Note 1) BOD33 threshold level Hysteresis OFF or BOD33 threshold level Hysteresis ON LEVEL[7:0] = 0x00 (min) 1.39 1.510 1.62 V LEVEL[7:0]= 0x19 (recommended value) 1.52 1.659 1.79 LEVEL[7:0] = 0x1C (fuse value) 1.54 1.677 1.
PAGE 2042
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-8. BOD33 Power Consumption Symbol CPU Mode Conditions TA IDD VCC = 1.8V Max 105°C Typ 25°C 8.52 Active / Idle Typ. Max Units 13.26 µA VCC = 3.3V 10.10 15.70 Standby with BOD continuous normal mode VCC = 1.8V 4.71 6.74 VCC = 3.3V 6.01 8.59 Standby with BOD continuous low power mode or Hibernate mode VCC = 1.8V 0.15 0.25 VCC = 3.3V 0.21 0.33 55.4.
PAGE 2043
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C ...........continued Symbol Parameters Ts Ts Conditions Min Typ SAMPCTRL.OFFCOMP=1 REFCTRL.REFCOMP=1 CTRLC.R2R=1 Sampling time with DAC as input Unit (4) SAMPCTRL.OFFCOMP=0 (3) REFCTRL.REFCOMP=0 CTRLC.R2R=0 Sampling time with Temp Sensor or Bandgap as input Max ns SAMPCTRL.OFFCOMP=1 REFCTRL.REFCOMP=1 CTRLC.R2R=1 10000 SAMPCTRL.OFFCOMP=0 (3) REFCTRL.REFCOMP=0 CTRLC.
PAGE 2044
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C ...........continued Symbol Gain Gain Offset Offset Parameter Gain Error with REFCTRL.REFCOMP=1 Gain Error with REFCTRL.REFCOMP=0 Offset Error with SAMPCTRL.OFFCOMP=1 Offset Error with SAMPCTRL.
PAGE 2045
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C ...........continued Symbol Parameter TUE Total Unadjusted Error (3) Fadc = 1Msps - R2R disabled INL Integral Non Linearity Fadc = 1Msps - R2R disabled DNL Differential Non Linearity Fadc = 1Msps - R2R disabled Gain Offset Gain Error with REFCTRL.REFCOMP=1 Offset Error with SAMPCTRL.
PAGE 2046
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-12. Power Consumption Symbol Parameters Conditions Ta Typ. Max Units fs = 1 Msps / Reference buffer disabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA = VREF = 3.0V Differential mode IDD VDDANA Single Ended mode 279 326 482 686 28 85 fs = 10 ksps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA = VREF = 3.
PAGE 2047
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-14. Single-Ended Mode (1) Symbol Parameters Conditions Min. Typ. Max. i12clk=12 MHz VDDANA = 3.0V - External Ref = 2.0V - ±2.7 ±4.0 - ±5.2 ±8.7 Unit Cload = 50pF INL Integral Non Linearity, Best Fit curve from 0x080 to 0xF7F i12clk=12 MHz VDDANA = 3.0V - 1V Internal Ref Cload = 50pF LSB i12clk=12 MHz VDDANA = 3.0V - External Ref = 2.0V - ±3.5 ±6.1 - ±6.4 ±9.4 External Reference voltage - ±0.3 ±1.6 1.
PAGE 2048
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Note: 1. Hysteresis disabled. Table 55-17. Power Consumption Symbol Parameters Conditions Ta IDDANA COMPCTRLn.SPEED=0x3, VDDANA=3.3V Max.105°C 59 Typ.25°C Current consumption for One AC enabled, Hysteresis disabled voltage scaler disabled Typ. Max. Unit Current consumption Voltage Scaler only VDDANA=3.3V 55.4.
PAGE 2049
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Table 55-18. Power Consumption (1) Symbol PTC scan rate (msec) Parameters Oversamples 10 50 IDD 137 2174 16 146 2194 4 77 2098 79 2104 68 2092 16 69 2095 4 64 2086 16 65 2089 4 100 200 Typ. Max Units 4 16 Current Consumption Ta Max 105°C Typ 25°C µA Note: 1. These are based on characterization. 55.5 NVM Characteristics Table 55-19.
PAGE 2050
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C 55.6 Oscillators Characteristics (105°C) 55.6.1 Crystal Oscillator (XOSC) Characteristics (105°C) Table 55-20. Multiple Crystal Oscillator Electrical Characteristics Symbol Parameter Tstart Startup time Conditions Min. Typ.
PAGE 2051
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C 55.6.3 Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics (105°C) Table 55-23. Ultra-Low-Power Internal 32 kHz RC Oscillator Electrical Characteristics Symbol Parameter FOUT Calibration Output frequency Factory default & without user software calibration With user software calibration Conditions Min. Typ. Max Units [-40, +105]°C, VDDANA>1.71V 26.00 32.768 39.
PAGE 2052
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 105°C Note: 1. These are based on simulation. These values are not covered by test or characterization. 2. These FDPLL200M characteristics are applicable with LDO regulator and a direct reference (i.e., REFCLK is XOSC or XOSC32K, not GCLK). Table 55-27. Power Consumption Symbol Parameter Conditions TA Typ. Max. Units IDD Current Consumption Ck = 96 MHz, VDD = 3.3V Max. 105°C Typ. 25°C 0.9 1.8 mA 2.0 2.6 Ck = 200 MHz, VDD = 3.
PAGE 2053
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C 56. Electrical Characteristics at 125°C The specifications for 125°C temperature devices are identical to those shown in 54. Electrical Characteristics at 85°C, with the exception of the parameters listed in this chapter. 56.1 General Operating Ratings (125°C) The device must operate within the ratings listed below in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 56-1.
PAGE 2054
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Note: 1. VIL source < (VSS - 0.6). Characterized but not tested. 2. VIH source > (VDDIO + 0.6) for non-5V tolerant pins only. 3. Digital 5V tolerant pins do not have an internal high side diode to VDDIO, and therefore, cannot tolerate any “positive” input injection current. 4. Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDDIO + 0.6) or VIL source < (GND - 0.6)). 5.
PAGE 2055
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C ...........continued Symbol Description Max. Units fGCLK_TCCx, x = {0, ... , 4} TCCx input clock frequency 180 MHz fGCLK_TCx, x = {0, ...
PAGE 2056
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-5. Active Current Consumption - Active Mode Mode conditions Regulator Clock FDPLL 100 MHz LDO DFLL 48 MHz XOSC 32 MHz ACTIVE COREMARK (1) FDPLL 120 MHz BUCK DFLL 48 MHz XOSC 32 MHz FDPLL 100 MHz LDO DFLL 48 MHz XOSC 32 MHz IDLE NA FDPLL 100 MHz BUCK DFLL 48 MHz XOSC 32 MHz VDD Typ. Max. 1.8 136 229 3.3 137 232 1.8 136 370 3.3 136 371 1.8 146 611 3.3 149 613 1.8 103 215 3.3 65 176 1.
PAGE 2057
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-6. Standby, Hibernate, Backup and Off Mode Current Consumption Conditions Regulator Mode fast wake-up disabled (PM.STDBYCFG.FASTWKUP=0x0), no peripheral running LDO Mode No System RAM retained (PM.STDBYCFG.RAMCFG=0x2). 8KB backup RAM retained BUCK fast wake-up enabled (PM.STDBYCFG.FASTWKUP=0x3), no peripheral running LDO No System RAM retained (PM.STDBYCFG.RAMCFG=0x2).
PAGE 2058
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C ...........continued Mode Regulator Mode Conditions Typ. Max. 1.8V 6 316 3.3V 6 320 1.8V 3 216 3.3V 3 221 1.8V 6 318 3.3V 7 322 1.8V 3 217 3.3V 3 223 1.8V 7 359 3.3V 8 364 1.8V 3 244 4 250 7 400 3.3V 8 405 1.8V 4 273 3.3V 4 279 1.8V 9 636 3.3V 10 641 1.8V 5 430 3.3V 4 434 1.8V 16 1574 3.3V 17 1578 1.8V 9 1061 3.
PAGE 2059
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C 56.6 Analog Characteristics (125°C) 56.6.1 Power-On Reset (POR) Characteristics (125°C) Table 56-7. POR Characteristics Symbol Parameters Min. Typ. Max. Unit VPOT+ Voltage threshold Level on VDDIO rising 1.52 1.58 1.65 V VPOT- Voltage threshold Level on VDDIO falling 0.97 1.26 1.36 V VDD Figure 56-1. POR Operating Principle VPOT+ VPOT- Reset Time Note: The shaded area indicates that the device is in a Reset state.
PAGE 2060
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-8. BOD33 Characteristics on VDD and VBAT Monitoring in Normal Mode (During Power-up Phase and Active Mode) Symbol Parameters Conditions (see Notes 3, 4) Min Typ Max Unit VBOD or VBOD( see Note 1) BOD33 threshold level Hysteresis OFF or BOD33 threshold level Hysteresis ON LEVEL[7:0] = 0x00 (min) 1.45 1.50 1.55 V LEVEL[7:0] = 0x19 (recommended value) 1.6 1.65 1.71 LEVEL[7:0]= 0x1C (fuse value) 1.62 1.67 1.
PAGE 2061
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-9. BOD33 Characteristics on VDD and VBAT Monitoring in Low-Power Mode (During Standby/Backup/Hibernate Modes) Symbol Parameters Conditions (see Notes 3, 4) Min Typ Max Unit VBOD or VBOD( see Note 1) BOD33 threshold level Hysteresis OFF or BOD33 threshold level Hysteresis ON LEVEL[7:0] = 0x00 (min) 1.39 1.510 1.62 V LEVEL[7:0]= 0x19 (recommended value) 1.52 1.659 1.79 LEVEL[7:0] = 0x1C (fuse value) 1.54 1.677 1.
PAGE 2062
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-10. BOD33 Power Consumption Symbol CPU Mode Conditions TA IDD VCC = 1.8V Max 125°C Typ 25°C 8.52 Active / Idle Typ. VCC = 3.3V 56.6.3 Max Units 13.9 µA 10.10 16.5 Standby with BOD continuous normal VCC = 1.8V mode VCC = 3.3V 4.71 6.7 6.01 8.6 Standby with BOD continuous low power mode or Hibernate mode VCC = 1.8V 0.15 0.27 VCC = 3.3V 0.21 0.
PAGE 2063
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Note: 1. These values are based on characterization. These values are not covered by test limits in production. 2. All values expressed in decibel refer to the full scale input and are tested with an input signal 0.35dB below full scale; THD measured on the first seven harmonics of the input signal. 3. With REFCTRL.REFCOMP=1 and SAMPCTRL.OFFCOMP=1. Table 56-12.
PAGE 2064
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C ...........continued Symbol Offset Parameter Offset Error with SAMPCTRL.OFFCOMP=1 SFDR Spurious Free Dynamic Range SINAD Signal to Noise and Distortion ratio SNR Signal to Noise ratio THD Total Harmonic Distortion Nrms Noise RMS Conditions Fadc = 1Msps Fs = 1Msps Fin = 14kHz (2) constant input voltage Measurement Min Typ Max Vddana=3.0V Vref=Vddana -21 -7.2 +9.3 Vddana=3.0V ExtVref=2.0V -21 -3.3 +17 Vddana=3.
PAGE 2065
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-13. Power Consumption Symbol Parameters IDD VDDANA Differential mode Single Ended mode 56.6.4 Conditions Ta Typ. Max Units fs = 1 Msps / Reference buffer disabled / Max 125°C 279 848 BIASREFBUF = '111', BIASREFCOMP = Typ 25°C '111' VDDANA = VREF = 3.0V fs = 1 Msps / Reference buffer enabled / BIASREFBUF = '111', BIASREFCOMP = '111' VDDANA = VREF = 3.
PAGE 2066
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C ...........continued Symbol Parameters Offerr Offset Error ENOB Effective Number of Bits SNR Signal to Noise ratio THD Total Harmonic Distortion Conditions Min. Typ. Max. External Reference voltage - ±13 ±47 1.0V Internal Reference voltage - ±8 ±79 9.9 Fs = 1Ms/s - External Ref - CCTRL=0x2 Unit mV 10.7 10.9 63.5 68.6 72.6 dB -79.1 -72.5 -61.0 Note: 1. These values are based on characterization.
PAGE 2067
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-16. Power Consumption Symbol Parameters Conditions Ta IDDANA Differential Mode, DC supply current, 2 output channels without load fs = 1 Msps, CCTR L= 0x2, VREF > 2.4V, VCC = 3.3V Max. 125°C Typ. 25°C Single-Ended Mode, DC supply current, 2 output channels without load 56.6.5 Min. Typ. Max. Unit - 384 634 fs = 10 ksps, CCTRL = 0x0, VREF < 2.4V, VCC = 3.3V - 283 482 fs = 1 Msps, CCTRL = 0x2, VREF > 2.4V, VCC = 3.
PAGE 2068
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C CPU is running on Flash with 2 wait states, at 48 MHz PTC running at 4 MHz PTC Configuration Mutual Capacitance mode One touch channel System Configuration Standby Sleep mode enabled RTC running on ULP32K: used to define the PTC scan rate, through the event system RTC interrupts (wake up) the CPU to perform PTC scans Table 56-19.
PAGE 2069
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C 56.8 Oscillators Characteristics (125°C) 56.8.1 Crystal Oscillator (XOSC) Characteristics (125°C) Table 56-21. Multiple Crystal Oscillator Characteristics Symbol Parameter Tstart Startup time Conditions Min. Typ.
PAGE 2070
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C Table 56-24. Power Consumption Symbol Parameter Condition s Ta Gain Mode Typ. IDD Current VDD=3.0V consumptio n Max 125°C Std. Typ 25°C High Max. Units 1.5 2.6 µA 1.9 3.4 56.8.3 Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics (125°C) Table 56-25.
PAGE 2071
SAM D5x/E5x Family Data Sheet Electrical Characteristics at 125°C 56.8.5 Fractional Digital Phase Lock Loop (FDPLL) Characteristics (125°C) Table 56-28. Fractional Digital Phase Lock Loop Characteristics (1) Symbol Parameter Conditions Jp fIN = 32 kHz, fOUT = 96 MHz - 1.9 3.0 fIN = 32 kHz, fOUT = 200 MHz - 3.4 6.0 fIN = 3.2 MHz, fOUT = 96 MHz - 2.0 3.1 fIN = 3.2 MHz, fOUT = 200 MHz - 4.3 7.2 Period jitter (Peak-Peak value) Min. Typ. Max. Units % Note: 1.
PAGE 2072
SAM D5x/E5x Family Data Sheet AEC Q-100 Grade 1, 125°C Electrical Charac... 57. AEC Q-100 Grade 1, 125°C Electrical Characteristics Important: AEC-Q100 Grade 1 Electrical Specifications are covered by Electrical Characteristics at 125°C unless explicitly mentioned in this document. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Packaging Information 58. Packaging Information 58.1 Package Marking Information All devices are marked with Atmel logo and ordering code. Additional marking information is as follows: • "YY": Manufacturing year • "WW": Manufacturing week • "R": Internal Code • "XXXXXX": Lot number 58.2 Thermal Considerations 58.2.1 Thermal Resistance Data The following table summarizes the thermal resistance data depending on the package. Table 58-1. Thermal Resistance Data 58.2.
PAGE 2074
SAM D5x/E5x Family Data Sheet Packaging Information • θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device • PD = Device power consumption (W) • TA = Ambient temperature (°C) From the first equation, the user can derive the estimated lifetime of the chip and decide whether a cooling device is necessary or not. If a cooling device has to be fitted on the chip, the second equation must be used to compute the resulting average chip-junction temperature TJ in °C. 58.
PAGE 2075
SAM D5x/E5x Family Data Sheet Packaging Information 58.3.1 48-Pin VQFN Note: The exposed die attach pad is not connected electrically inside the device. Table 58-2. Device and Package Maximum Weight 140 mg Table 58-3. Package Characteristics Moisture Sensitivity Level MSL3 © 2019 Microchip Technology Inc.
PAGE 2076
SAM D5x/E5x Family Data Sheet Packaging Information Table 58-4. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Packaging Information 58.3.2 48-Pin VQFN Wettable Flanks 48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN] With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 48X 0.08 C D A 0.10 C D 4 B N E 4 1 2 NOTE 1 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C A1 0.
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SAM D5x/E5x Family Data Sheet Packaging Information 48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN] With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
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SAM D5x/E5x Family Data Sheet Packaging Information 48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN] With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
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SAM D5x/E5x Family Data Sheet Packaging Information Table 58-5. Device and Package Maximum Weight 14 mg Table 58-6. Package Characteristics Moisture Sensitivity Level MSL1 Table 58-7. Package Reference JEDEC Drawing Reference N/A JESD97 Classification e1 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Packaging Information 58.3.4 64-Pin VQFN Note: The exposed die attach pad is not connected electrically inside the device. Table 58-8. Device and Package Maximum Weight 200 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Packaging Information Table 58-9. Package Charateristics Moisture Sensitivity Level MSL3 Table 58-10. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Packaging Information 58.3.5 64-Pin VQFN Wettable Flanks 64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN] With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 64X 0.08 C D NOTE 1 0.10 C A B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C 0.05 0.20 0.10 C A B 0.
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SAM D5x/E5x Family Data Sheet Packaging Information 64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN] With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
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SAM D5x/E5x Family Data Sheet Packaging Information 64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN] With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
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SAM D5x/E5x Family Data Sheet Packaging Information 58.3.6 64-pin TQFP 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D NOTE 2 A B E1/2 E1 A E A SEE DETAIL 1 N 4X N/4 TIPS 0.20 C A-B D 1 3 2 4X NOTE 1 0.20 H A-B D TOP VIEW A2 A 0.05 C SEATING PLANE 0.08 C 64 X b 0.
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SAM D5x/E5x Family Data Sheet Packaging Information 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
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SAM D5x/E5x Family Data Sheet Packaging Information 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 E C2 G Y1 X1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X28) X1 Contact Pad Length (X28) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.
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SAM D5x/E5x Family Data Sheet Packaging Information 58.3.7 100 pin TQFP Table 58-11. Device and Package Maximum Weight 520 mg Table 58-12. Package Characteristics Moisture Sensitivity Level MSL3 Table 58-13. Package Reference JEDEC Drawing Reference MS-026, variant AED JESD97 Classification e3 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Packaging Information 58.3.8 120-ball TFBGA 120-Ball Thin Fine Pitch Ball Grid Array Package (DGB) - 8x8 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D NOTE 1 1 (DATUM A) (DATUM B) 2X 0.10 C 2 3 4 5 6 7 8 A 9 10 11 12 13 14 B 15 A B C D E F G H J K L M N P R E 2X TOP VIEW 0.
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SAM D5x/E5x Family Data Sheet Packaging Information 120-Ball Thin Fine Pitch Ball Grid Array Package (DGB) - 8x8 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.10 C (A3) (A2) A1 120X 0.
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SAM D5x/E5x Family Data Sheet Packaging Information 120-Ball Thin Fine Pitch Ball Grid Array Package (DGB) - 8x8 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
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SAM D5x/E5x Family Data Sheet Packaging Information 58.3.9 128 pin TQFP Table 58-14. Device and Package Maximum Weight 520 mg Table 58-15. Package Characteristics Moisture Sensitivity Level MSL3 © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Packaging Information Table 58-16. Package Reference 58.4 JEDEC Drawing Reference MS-026 JESD97 Classification E3 Soldering Profile The following table gives the recommended soldering profile from J-STD-20. Table 58-17. Recommended Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to peak) 3°C/s max.
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SAM D5x/E5x Family Data Sheet Schematic Checklist 59. 59.1 Schematic Checklist Introduction This chapter describes a common checklist which should be used when starting and reviewing the schematics for a SAM D5x/E5x design. This chapter illustrates recommended power supply connections, how to connect external analog references, programmer, debugger, oscillator and crystal. 59.1.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-1. Power Supply Connection for Switching/Linear Mode Close to device (for every pin) IO Supply (1.71V — 3.63V) SAM Device VBAT (PB03) VDDIOB Main Supply (1.71V — 3.63V) VDDANA VDDIO 10µH 100nF 100nF 1µF 10µF VSW 10µF VDDCORE 4.7µF 100nF GND GNDANA Figure 59-2. Power Supply Connection for Linear Mode Only Close to device (for every pin) IO Supply (1.71V — 3.63V) SAM Device VDDIOB VBAT (PB03) Main Supply (1.71V — 3.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-3. Power Supply Connection for Battery Backup Close to device (for every pin) IO Supply (1.71V — 3.63V) SAM E54 VDDIOB VBAT (PB03) Main Supply (1.71V — 3.63V) VDDANA VDDIO 100nF 10µH 100nF 100nF 1µF 10µF VSW 10µF VDDCORE 4.7µF 100nF GND GNDANA Note: 1. The passive component value shown in figures 58-1, 58-2 & 58-3 is a typical example. Refer to 54.10.1 Voltage Regulator Characteristics for details on specification. 2.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-4. External Analog Reference Schematic With Three References Close to device (for every pin) VREFA EXTERNAL REFERENCE 1 4.7μF 100nF GND VREFB EXTERNAL REFERENCE 2 4.7μF 100nF GND VREFC EXTERNAL REFERENCE 3 © 2019 Microchip Technology Inc. 4.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-5. External Analog Reference Schematic With Two References Close to device (for every pin ) VREFA EXTERNAL REFERENCE 1 4.7μF 100 nF GND VREFB EXTERNAL REFERENCE 2 4.7μF 100 nF GND VREFC GND © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-6. External Analog Reference Schematic With One Reference Close to device (for every pin ) VREFA EXTERNAL REFERENCE 4.7μF 100 nF GND VREFB GND VREFC GND Table 59-1. External Analog Reference Connections Signal Name Recommended Pin Connection Description VREFx 1.0V to (VDDANA - 0.6V) for ADC 1.0V to (VDDANA - 0.6V) for DAC Decoupling/filtering capacitors 100nF(1)(2) and 4.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-7. External Reset Circuit Schematic VDD 10kΩ 330Ω RESET 100nF GND A pull-up resistor makes sure that the Reset does not go low and unintentionally causing a device Reset. An additional resistor has been added in series with the switch to safely discharge the filtering capacitor, i.e. preventing a current surge when shorting the filtering capacitor which again can cause a noise spike that can have a negative effect on the system. Table 59-2.
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SAM D5x/E5x Family Data Sheet Schematic Checklist 59.6.1 External Clock Source Figure 59-8. External Clock Source Schematic External Clock XIN XOUT/GPIO NC/GPIO Table 59-3. External Clock Source Connections 59.6.2 Signal Name Recommended Pin Connection Description XIN XIN is used as input for an external clock signal Input for inverting oscillator pin XOUT/GPIO Can be left unconnected or used as normal GPIO NC/GPIO Crystal Oscillator Figure 59-9.
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SAM D5x/E5x Family Data Sheet Schematic Checklist The typical parasitic load capacitance values are available in the Electrical Characteristics section. This capacitance and PCB capacitance can allow using a crystal inferior to 12.5pF load capacitance without external capacitors as shown in the next figure. Figure 59-10. External Real Time Oscillator without Load Capacitor XIN32 32.
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SAM D5x/E5x Family Data Sheet Schematic Checklist CL1 XIN CEL1 CL2 XOUT CP1 CP2 External Internal Figure 59-12. Crystal Circuit With Internal, External and Parasitic Capacitance CEL2 Using this model the total capacitive load for the crystal can be calculated as shown in the equation below: �tot = ��1 + ��1 + �EL1 ��2 + ��2 + �EL2 ��1 + ��1 + �EL1 + ��2 + ��2 + �EL2 where Ctot is the total load capacitance seen by the crystal.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Note: A pull-up resistor on the SWCLK pin is critical for reliable operation. Refer to related link for more information. Figure 59-13. SWCLK Circuit Connections VDD 1kΩ SWCLK Table 59-6. SWCLK Circuit Connections Pin Name Description Recommended Pin Connection SWCLK Serial wire clock pin Pull-up resistor 1kΩ Related Links 59.1.1 Operation in Noisy Environment 59.7.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-14. Cortex Debug Connector (10-pin) VDD Cortex Debug Connector (10-pin) VTref SWDIO 1 GND GND NC NC RESET SWDCLK NC SWCLK NC RESET SWDIO GND Table 59-7. Cortex Debug Connector (10-pin) 59.7.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-15. 20-pin IDC JTAG Connector VDD 20-pin IDC JTAG Connector VCC NC NC SWDIO 1 NC GND RESET GND GND SWDCLK GND NC GND NC GND* RESET GND* NC GND* NC GND* SWCLK SWDIO GND Table 59-8. 20-pin IDC JTAG Connector Header Signal Name Description 59.7.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Figure 59-16. Trace (CoreSight 20) Connector Diagram 59.8 QSPI Interface Table 59-9.
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SAM D5x/E5x Family Data Sheet Schematic Checklist Table 59-10. USB Interface Checklist Signal Name D+ D- Recommended Pin Connection Description • The impedance of the pair should be matched on the PCB to minimize reflections. • USB differential tracks should be routed with the same characteristics (length, width, number of vias, etc.) • For a tightly coupled differential pair,the signal routing should be as parallel as possible, with a minimum number of angles and vias.
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SAM D5x/E5x Family Data Sheet Schematic Checklist 59.10 SDHC Interface The SD/MMC Host Controller (SDHC) is compliant with the SD Host Controller Standard specifications. There are two instances of SDHC available on this device: SDHC0 and SDHC1. The typical connection diagram is shown in the following figure. © 2019 Microchip Technology Inc.
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SAM D5x/E5x Family Data Sheet Conventions 60. Conventions 60.1 Numerical Notation Table 60-1. Numerical Notation 60.2 Symbol Description 165 Decimal number 0b0101 Binary number (example 0b0101 = 5 decimal) '0101' Binary numbers are given without prefix if unambiguous 0x3B24 Hexadecimal number X Represents an unknown or do not care value Z Represents a high-impedance (floating) state for either a signal or a bus Memory Size and Type Table 60-2. Memory Size and Bit Rate 60.
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SAM D5x/E5x Family Data Sheet Conventions ...........continued 60.4 Symbol Description KHz 1 KHz = 1,024 Hz, 32 KHz = 32,768 Hz MHz 1 MHz = 106 Hz = 1,000,000 Hz GHz 1 GHz = 109 Hz = 1,000,000,000 Hz s second ms millisecond µs microsecond ns nanosecond Registers and Bits Table 60-4. Register and Bit Mnemonics Symbol Description R/W Read/Write accessible register bit. The user can read from and write to this bit. R Read-only accessible register bit. The user can only read this bit.
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SAM D5x/E5x Family Data Sheet Conventions ...........continued Symbol Description SET/CLR Registers with SET/CLR suffix allows the user to clear and set bits in a register without doing a read-modify-write operation. These registers always come in pairs. Writing a ‘1’ to a bit in the CLR register will clear the corresponding bit in both registers, while writing a ‘1’ to a bit in the SET register will set the corresponding bit in both registers. Both registers will return the same value when read.
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SAM D5x/E5x Family Data Sheet Acronyms and Abbreviations 61. Acronyms and Abbreviations The below table contains acronyms and abbreviations used in this document. Table 61-1.
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SAM D5x/E5x Family Data Sheet Acronyms and Abbreviations ...........
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SAM D5x/E5x Family Data Sheet Acronyms and Abbreviations ...........
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SAM D5x/E5x Family Data Sheet Revision History 62. Revision History Table 62-1.
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SAM D5x/E5x Family Data Sheet Revision History ...........
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SAM D5x/E5x Family Data Sheet Revision History ...........
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SAM D5x/E5x Family Data Sheet Revision History ...........continued Section Name or Type Change Description Electrical Characteristics at 125°C Updated the following sections: • Power Consumption • Analog-To-Digital Characteristics • Digital-to-Analog Characteristics Added new section: • PTC Characteristics Table 62-2. Rev. D - 12/2018 Section Name or Type Change Description Ordering Information Added AEC-Q100 Qualified package type.
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SAM D5x/E5x Family Data Sheet Revision History ...........continued Section Name or Type Change Description EVSYS Corrected typographical errors in the USERm Register offset. CCL 1. 2. ADC TC Added clarification for INTREF to 45.8.6 Reference Control(REFCTRL). 1. 2. 3. TCC - Timer/Counter for Control Applications 1. 2. 3. 4. 5. 6. © 2019 Microchip Technology Inc. Internal Events Inputs Selection (EVENT) section was updated by removing ASYNCEVENT related information.
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SAM D5x/E5x Family Data Sheet Revision History ...........continued Section Name or Type 54. Electrical Characteristics at 85°C Change Description 1. 2. 3. 4. 5. 6. 7. 8. 9. Clarified how CLEXT can be computed in section 54.12.1 Crystal Oscillator (XOSC) Characteristics and 54.12.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics Clarified capacitor requirements in Table 54-18. External Components Requirements in Switching Mode and Table 54-19 Decoupling Requirements.
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SAM D5x/E5x Family Data Sheet Revision History ...........continued Section Name or Type Change Description Pinout Added the 120-ball TFBGA package pinout diagram. Multiplexed Signals Added 120-ball TFBGA and updated Note 3 (see Table 6-1. OSC32KCTRL - 32 kHz Oscillators Controller Added the EN1K and EN32K bits to the OSCULP32K register (see 29.8.9 OSCULP32K). SERCOM - Serial Communication Interface Added Fractional Baud information to the Baud Rate Equations (see Table 33-2).
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SAM D5x/E5x Family Data Sheet The Microchip Web Site Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers.
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SAM D5x/E5x Family Data Sheet Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
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SAM D5x/E5x Family Data Sheet application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use.
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SAM D5x/E5x Family Data Sheet analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2019 Microchip Technology Inc.
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