Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 50
Table 48: Sample Window
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
T
SAMP
Sampling error at receiver pins.
(1)
0.64 0.70 0.70 ns
T
SAMP_BUFIO
Sampling error at receiver pins using BUFIO.
(2)
0.40 0.46 0.46 ns
Notes:
1. This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation.
These measurements do not include package or clock tree skew.
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