Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 48
Table 45: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol Description Device
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.
(1)(2)
T
PSMMCMCC
/
T
PHMMCMCC
No delay clock-capable clock input and
IFF
(3)
with MMCM.
XC7S6 2.73/–0.59 3.27/–0.59 3.27/–0.59 ns
XC7S15 2.73/–0.59 3.27/–0.59 3.27/–0.59 ns
XC7S25 2.69/–0.61 3.21/–0.61 3.21/–0.61 ns
XC7S50 2.81/–0.62 3.35/–0.62 3.35/–0.62 ns
XC7S75 2.81/–0.62 3.36/–0.62 3.36/–0.62 ns
XC7S100 2.81/–0.62 3.36/–0.62 3.36/–0.62 ns
XA7S6 2.73/–0.59 3.27/–0.59 N/A ns
XA7S15 2.73/–0.59 3.27/–0.59 N/A ns
XA7S25 2.69/–0.61 3.21/–0.61 N/A ns
XA7S50 2.81/–0.62 3.35/–0.62 N/A ns
XA7S75 2.81/–0.62 3.36/–0.62 N/A ns
XA7S100 2.81/–0.62 3.36/–0.62 N/A ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock
input signal using the fastest process, lowest temperature, and highest voltage.
2. Use IBIS to determine any duty-cycle distortion incurred using various standards.
3. IFF = Input flip-flop or latch.
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