Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 44
Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
(1)
Symbol Description Device
V
CCINT
Operating Voltage and
Speed Grade
Units
1.0V 0.95V
-2 -1 -1L
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
T
ICKOFFAR
Clock-capable clock input and OUTFF at
pins/banks farthest from the BUFGs without
MMCM/PLL (far clock region).
(2)
XC7S6 5.55 6.50 6.50 ns
XC7S15 5.55 6.50 6.50 ns
XC7S25 5.55 6.44 6.44 ns
XC7S50 5.71 6.62 6.62 ns
XC7S75 6.01 7.02 7.02 ns
XC7S100 6.01 7.02 7.02 ns
XA7S6 5.55 6.50 N/A ns
XA7S15 5.55 6.50 N/A ns
XA7S25 5.55 6.44 N/A ns
XA7S50 5.71 6.62 N/A ns
XA7S75 6.01 7.02 N/A ns
XA7S100 6.01 7.02 N/A ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4].
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