Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 41
PLL Switching Characteristics
T
MMCMDCK_PSINCDEC
/
T
MMCMCKD_PSINCDEC
Setup and hold of phase-shift
increment/decrement.
1.04/0.00 1.04/0.00 1.04/0.00 ns
T
MMCMCKO_PSDONE
Phase shift clock-to-out of PSDONE. 0.680.810.81 ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
T
MMCMDCK_DADDR
/
T
MMCMCKD_DADDR
DADDR setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
T
MMCMDCK_DI
/
T
MMCMCKD_DI
DI setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
T
MMCMDCK_DEN
/
T
MMCMCKD_DEN
DEN setup/hold. 1.97/0.00 2.29/0.00 2.29/0.00 ns, Min
T
MMCMDCK_DWE
/
T
MMCMCKD_DWE
DWE setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
T
MMCMCKO_DRDY
CLK to out of DRDY. 0.72 0.99 0.99 ns, Max
F
DCK
DCLK frequency. 200.00 200.00 200.00 MHz, Max
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard [Ref 8].
4. Includes global clock buffer.
5. Calculated as F
VCO
/128 assuming output duty cycle is 50%.
6. When CLKOUT4_CASCADE = TRUE, MMCM_F
OUTMIN
is 0.036 MHz.
Table 38: PLL Specification
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
PLL_F
INMAX
Maximum input clock frequency. 800.00 800.00 800.00 MHz
PLL_F
INMIN
Minimum input clock frequency. 19.00 19.00 19.00 MHz
PLL_F
INJITTER
Maximum input clock period jitter. < 20% of clock input period or 1 ns Max
PLL_F
INDUTY
Allowable input duty cycle: 19—49 MHz. 25 25 25 %
Allowable input duty cycle: 50—199 MHz. 30 30 30 %
Allowable input duty cycle: 200—399 MHz. 35 35 35 %
Allowable input duty cycle: 400—499 MHz. 40 40 40 %
Allowable input duty cycle: >500 MHz. 45 45 45 %
PLL_F
VCOMIN
Minimum PLL VCO frequency. 800.00 800.00 800.00 MHz
PLL_F
VCOMAX
Maximum PLL VCO frequency. 1866.00 1600.00 1600.00 MHz
Table 37: MMCM Specification (Cont’d)
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
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