Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 36
T
DSPDCK_CEM_MREG
/
T
DSPCKD_CEM_MREG
CEM input to M register CLK.
0.21/
0.20
0.27/
0.23
0.27/
0.23
ns
T
DSPDCK_CEP_PREG
/
T
DSPCKD_CEP_PREG
CEP input to P register CLK.
0.43/
0.01
0.53/
0.01
0.53/
0.01
ns
Setup and Hold Times of the RST Pins
T
DSPDCK_{RSTA; RSTB}_{AREG; BREG}
/
T
DSPCKD_{RSTA; RSTB}_{AREG; BREG}
{RSTA, RSTB} input to {A, B} register CLK.
0.46/
0.13
0.55/
0.15
0.55/
0.15
ns
T
DSPDCK_RSTC_CREG
/
T
DSPCKD_RSTC_CREG
RSTC input to C register CLK.
0.08/
0.11
0.09/
0.12
0.09/
0.12
ns
T
DSPDCK_RSTD_DREG
/
T
DSPCKD_RSTD_DREG
RSTD input to D register CLK
0.50/
0.08
0.59/
0.09
0.59/
0.09
ns
T
DSPDCK_RSTM_MREG
/
T
DSPCKD_RSTM_MREG
RSTM input to M register CLK
0.23/
0.24
0.27/
0.28
0.27/
0.28
ns
T
DSPDCK_RSTP_PREG
/
T
DSPCKD_RSTP_PREG
RSTP input to P register CLK
0.30/
0.01
0.35/
0.01
0.35/
0.01
ns
Combinatorial Delays from Input Pins to Output Pins
T
DSPDO_A_CARRYOUT_MULT
A input to CARRYOUT output using multiplier. 4.35 5.18 5.18 ns
T
DSPDO_D_P_MULT
D input to P output using multiplier. 4.26 5.07 5.07 ns
T
DSPDO_B_P
B input to P output not using multiplier. 1.75 2.08 2.08 ns
T
DSPDO_C_P
C input to P output. 1.53 1.82 1.82 ns
Combinatorial Delays from Input Pins to Cascading Output Pins
T
DSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT} output. 0.63 0.74 0.74 ns
T
DSPDO_{A, B}_CARRYCASCOUT_MULT
{A, B} input to CARRYCASCOUT output using
multiplier.
4.65 5.54 5.54 ns
T
DSPDO_D_CARRYCASCOUT_MULT
D input to CARRYCASCOUT output using
multiplier.
4.54 5.40 5.40 ns
T
DSPDO_{A, B}_CARRYCASCOUT
{A, B} input to CARRYCASCOUT output not
using multiplier.
2.03 2.41 2.41 ns
T
DSPDO_C_CARRYCASCOUT
C input to CARRYCASCOUT output. 1.81 2.15 2.15 ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
T
DSPDO_ACIN_P_MULT
ACIN input to P output using multiplier. 4.19 5.00 5.00 ns
T
DSPDO_ACIN_P
ACIN input to P output not using multiplier. 1.57 1.88 1.88 ns
T
DSPDO_ACIN_ACOUT
ACIN input to ACOUT output. 0.44 0.53 0.53 ns
T
DSPDO_ACIN_CARRYCASCOUT_MULT
ACIN input to CARRYCASCOUT output using
multiplier.
4.47 5.33 5.33 ns
T
DSPDO_ACIN_CARRYCASCOUT
ACIN input to CARRYCASCOUT output not
using multiplier.
1.85 2.21 2.21 ns
T
DSPDO_PCIN_P
PCIN input to P output. 1.28 1.52 1.52 ns
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
V
CCINT
Operating
Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
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