Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 35
DSP48E1 Switching Characteristics
Table 31: DSP48E1 Switching Characteristics
Symbol Description
V
CCINT
Operating
Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T
DSPDCK_A_AREG
/
T
DSPCKD_A_AREG
A input to A register CLK.
0.30/
0.13
0.37/
0.14
0.37/
0.14
ns
T
DSPDCK_B_BREG
/
T
DSPCKD_B_BREG
B input to B register CLK.
0.38/
0.16
0.45/
0.18
0.45/
0.18
ns
T
DSPDCK_C_CREG
/
T
DSPCKD_C_CREG
C input to C register CLK.
0.20/
0.19
0.24/
0.21
0.24/
0.21
ns
T
DSPDCK_D_DREG
/
T
DSPCKD_D_DREG
D input to D register CLK.
0.32/
0.27
0.42/
0.27
0.42/
0.27
ns
T
DSPDCK_ACIN_AREG
/
T
DSPCKD_ACIN_AREG
ACIN input to A register CLK.
0.27/
0.13
0.32/
0.14
0.32/
0.14
ns
T
DSPDCK_BCIN_BREG
/
T
DSPCKD_BCIN_BREG
BCIN input to B register CLK.
0.29/
0.16
0.36/
0.18
0.36/
0.18
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T
DSPDCK_{A, B}_MREG_MULT
/
T
DSPCKD_{A, B}_MREG_MULT
{A, B} input to M register CLK using
multiplier.
2.76/
–0.01
3.29/
–0.01
3.29/
–0.01
ns
T
DSPDCK_{A, D}_ADREG
/
T
DSPCKD_{A, D}_ADREG
{A, D} input to AD register CLK.
1.48/
–0.02
1.76/
–0.02
1.76/
–0.02
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T
DSPDCK_{A, B}_PREG_MULT
/
T
DSPCKD_{A, B} _PREG_MULT
{A, B} input to P register CLK using
multiplier.
4.60/
–0.28
5.48/
–0.28
5.48/
–0.28
ns
T
DSPDCK_D_PREG_MULT
/
T
DSPCKD_D_PREG_MULT
D input to P register CLK using multiplier.
4.50/
–0.73
5.35/
–0.73
5.35/
–0.73
ns
T
DSPDCK_{A, B} _PREG
/
T
DSPCKD_{A, B} _PREG
A or B input to P register CLK not using
multiplier.
1.98/
–0.28
2.35/
–0.28
2.35/
–0.28
ns
T
DSPDCK_C_PREG
/
T
DSPCKD_C_PREG
C input to P register CLK not using multiplier.
1.76/
–0.26
2.10/
–0.26
2.10/
–0.26
ns
T
DSPDCK_PCIN_PREG
/
T
DSPCKD_PCIN_PREG
PCIN input to P register CLK.
1.51/
–0.15
1.80/
–0.15
1.80/
–0.15
ns
Setup and Hold Times of the CE Pins
T
DSPDCK_{CEA;CEB}_{AREG;BREG}
/
T
DSPCKD_{CEA;CEB}_{AREG;BREG}
{CEA; CEB} input to {A; B} register CLK.
0.42/
0.08
0.52/
0.11
0.52/
0.11
ns
T
DSPDCK_CEC_CREG
/
T
DSPCKD_CEC_CREG
CEC input to C register CLK.
0.34/
0.11
0.42/
0.13
0.42/
0.13
ns
T
DSPDCK_CED_DREG
/
T
DSPCKD_CED_DREG
CED input to D register CLK.
0.43/
–0.03
0.52/
–0.03
0.52/
–0.03
ns
Send Feedback