Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 34
F
MAX_CAS_RF_
DELAYED_WRITE
When in cascade RF mode and there is a
possibility of address overlap between
port A and port B.
362.19 297.35 297.35 MHz
F
MAX_FIFO
FIFO in all modes without ECC. 460.83 388.20 388.20 MHz
F
MAX_ECC
Block RAM and FIFO in ECC
configuration.
365.10 297.53 297.53 MHz
Notes:
1. T
RCKO_DOR
includes T
RCKO_DOW
, T
RCKO_DOPR
, and T
RCKO_DOPW
as well as the B port equivalent timing parameters.
2. These parameters also apply to synchronous FIFO with DO_REG = 0.
3. T
RCKO_DO
includes T
RCKO_DOP
as well as the B port equivalent timing parameters.
4. These parameters also apply to multi-rate (asynchronous) and synchronous FIFO with DO_REG = 1.
5. T
RCKO_FLAGS
includes the following parameters: T
RCKO_AEMPTY
, T
RCKO_AFULL
, T
RCKO_EMPTY
, T
RCKO_FULL
, T
RCKO_RDERR
, T
RCKO_WRERR
.
6. T
RCKO_POINTERS
includes both T
RCKO_RDCOUNT
and T
RCKO_WRCOUNT
.
7. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
8. These parameters include both A and B inputs as well as the parity inputs of A and B.
9. T
RCO_FLAGS
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
10. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
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