Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 32
Block RAM and FIFO Switching Characteristics
Table 30: Block RAM and FIFO Switching Characteristics
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
Block RAM and FIFO Clock-to-Out Delays
T
RCKO_DO
and
T
RCKO_DO_REG
Clock CLK to DOUT output (without
output register).
(1)(2)
2.13 2.46 2.46 ns, Max
Clock CLK to DOUT output (with output
register).
(3)(4)
0.74 0.89 0.89 ns, Max
T
RCKO_DO_ECC
and
T
RCKO_DO_ECC_REG
Clock CLK to DOUT output with ECC
(without output register).
(1)(2)
3.04 3.84 3.84 ns, Max
Clock CLK to DOUT output with ECC
(with output register).
(3)(4)
0.81 0.94 0.94 ns, Max
T
RCKO_DO_CASCOUT
and
T
RCKO_DO_CASCOUT_REG
Clock CLK to DOUT output with cascade
(without output register).
(1)
2.88 3.30 3.30 ns, Max
Clock CLK to DOUT output with cascade
(with output register).
(3)
1.28 1.46 1.46 ns, Max
T
RCKO_FLAGS
Clock CLK to FIFO flags outputs.
(5)
0.87 1.05 1.05 ns, Max
T
RCKO_POINTERS
Clock CLK to FIFO pointers outputs.
(6)
1.02 1.15 1.15 ns, Max
T
RCKO_PARITY_ECC
Clock CLK to ECCPARITY in ECC encode
only mode.
0.85 0.94 0.94 ns, Max
T
RCKO_SDBIT_ECC
and
T
RCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without output
register).
2.81 3.55 3.55 ns, Max
Clock CLK to BITERR (with output
register).
0.76 0.89 0.89 ns, Max
T
RCKO_RDADDR_ECC
and
T
RCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC
(without output register).
0.88 1.07 1.07 ns, Max
Clock CLK to RDADDR output with ECC
(with output register).
0.93 1.08 1.08 ns, Max
Setup and Hold Times Before/After Clock CLK
T
RCCK_ADDRA
/
T
RCKC_ADDRA
ADDR inputs.
(7)
0.49/0.33 0.57/0.36 0.57/0.36 ns, Min
T
RDCK_DI_WF_NC
/
T
RCKD_DI_WF_NC
Data input setup/hold time when block
RAM is configured in WRITE_FIRST or
NO_CHANGE mode.
(8)
0.65/0.63 0.74/0.67 0.74/0.67 ns, Min
T
RDCK_DI_RF
/
T
RCKD_DI_RF
Data input setup/hold time when block
RAM is configured in READ_FIRST
mode.
(8)
0.22/0.34 0.25/0.41 0.25/0.41 ns, Min
T
RDCK_DI_ECC
/
T
RCKD_DI_ECC
DIN inputs with block RAM ECC in
standard mode.
(8)
0.55/0.46 0.63/0.50 0.63/0.50 ns, Min
T
RDCK_DI_ECCW
/
T
RCKD_DI_ECCW
DIN inputs with block RAM ECC encode
only.
(8)
1.02/0.46 1.17/0.50 1.17/0.50 ns, Min
Send Feedback