Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 31
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 28: CLB Distributed RAM Switching Characteristics
Symbol Description
V
CCINT
Operating Voltage and
Speed Grade
Units
1.0V 0.95V
-2 -1 -1L
Sequential Delays
T
SHCKO
Clock to A – B outputs. 1.09 1.32 1.32 ns, Max
T
SHCKO_1
Clock to AMUX – BMUX outputs. 1.53 1.86 1.86 ns, Max
Setup and Hold Times Before/After Clock CLK
T
DS_LRAM
/T
DH_LRAM
A – D inputs to CLK. 0.60/0.30 0.72/0.35 0.72/0.35 ns, Min
T
AS_LRAM
/T
AH_LRAM
Address An inputs to clock. 0.30/0.60 0.37/0.70 0.37/0.70 ns, Min
Address An inputs through MUXs and/or
carry logic to clock.
0.77/0.21 0.94/0.26 0.94/0.26 ns, Min
T
WS_LRAM
/T
WH_LRAM
WE input to clock. 0.43/0.12 0.53/0.17 0.53/0.17 ns, Min
T
CECK_LRAM
/T
CKCE_LRAM
CE input to CLK. 0.44/0.11 0.53/0.17 0.53/0.17 ns, Min
Clock CLK
T
MPW_LRAM
Minimum pulse width. 1.13 1.25 1.25 ns, Min
T
MCP
Minimum clock period. 2.262.502.50ns, Min
Notes:
1. T
SHCKO
also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
Table 29: CLB Shift Register Switching Characteristics
Symbol Description
V
CCINT
Operating Voltage and
Speed Grade
Units
1.0V 0.95V
-2 -1 -1L
Sequential Delays
T
REG
Clock to A – D outputs. 1.33 1.61 1.61 ns, Max
T
REG_MUX
Clock to AMUX – DMUX output. 1.77 2.15 2.15 ns, Max
T
REG_M31
Clock to DMUX output via M31 output. 1.23 1.46 1.46 ns, Max
Setup and Hold Times Before/After Clock CLK
T
WS_SHFREG
/ T
WH_SHFREG
WE input. 0.41/0.12 0.51/0.17 0.51/0.17 ns, Min
T
CECK_SHFREG
/
T
CKCE_SHFREG
CE input to CLK. 0.42/0.11 0.52/0.17 0.52/0.17 ns, Min
T
DS_SHFREG
/ T
DH_SHFREG
A – D inputs to CLK. 0.37/0.37 0.44/0.43 0.44/0.43 ns, Min
Clock CLK
T
MPW_SHFREG
Minimum pulse width. 0.86 0.98 0.98 ns, Min
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