Datasheet

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 28
Input/Output Delay Switching Characteristics
Table 25: Input/Output Delay Switching Characteristics
Symbol Description
V
CCINT
Operating Voltage and
Speed Grade
Units
1.0V 0.95V
-2 -1 -1L
IDELAYCTRL
T
DLYCCO_RDY
Reset to ready for IDELAYCTRL. 3.67 3.67 3.67 µs
F
IDELAYCTRL_REF
Attribute REFCLK frequency = 200.00.
(1)
200.00 200.00 200.00 MHz
Attribute REFCLK frequency = 300.00.
(1)
300.00 300.00 300.00 MHz
Attribute REFCLK frequency = 400.00.
(1)
400.00 N/A N/A MHz
IDELAYCTRL_REF_
PRECISION
REFCLK precision ±10 ±10 ±10 MHz
T
IDELAYCTRL_RPW
Minimum reset pulse width. 59.28 59.28 59.28 ns
IDELAY
T
IDELAYRESOLUTION
IDELAY chain delay resolution. 1/(32 x 2 x F
REF
)µs
T
IDELAYPAT_JIT
Pattern dependent period jitter in delay chain for
clock pattern.
(2)
000
ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23).
(3)
±5 ±5 ±5
ps
per tap
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23).
(4)
±9 ±9 ±9
ps
per tap
T
IDELAY_CLK_MAX
Maximum frequency of CLK input to IDELAY. 680.00 600.00 600.00 MHz
T
IDCCK_CE
/
T
IDCKC_CE
CE pin setup/hold with respect to C for IDELAY. 0.16/0.13 0.21/0.16 0.21/0.16 ns
T
IDCCK_INC
/
T
IDCKC_INC
INC pin setup/hold with respect to C for IDELAY. 0.14/0.18 0.16/0.22 0.16/0.22 ns
T
IDCCK_RST
/
T
IDCKC_RST
RST pin setup/hold with respect to C for IDELAY. 0.16/0.11 0.18/0.14 0.18/0.14 ns
T
IDDO_IDATAIN
Propagation delay through IDELAY. Note 5 Note 5 Note 5 ps
Notes:
1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.
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