Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 27
Output Serializer/Deserializer Switching Characteristics
Table 24: OSERDES Switching Characteristics
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
Setup/Hold
T
OSDCK_D
/
T
OSCKD_D
D input setup/hold with respect to CLKDIV. 0.45/0.03 0.63/0.03 0.63/0.03 ns
T
OSDCK_T
/
T
OSCKD_T
T input setup/hold with respect to CLK. 0.73/–0.13 0.88/–0.13 0.88/–0.13 ns
T
OSDCK_T2
/
T
OSCKD_T2
T input setup/hold with respect to CLKDIV. 0.34/–0.13 0.39/–0.13 0.39/–0.13 ns
T
OSCCK_OCE
/
T
OSCKC_OCE
OCE input setup/hold with respect to CLK. 0.34/0.58 0.51/0.58 0.51/0.58 ns
T
OSCCK_S
SR (reset) input setup with respect to CLKDIV. 0.52 0.85 0.85 ns
T
OSCCK_TCE
/
T
OSCKC_TCE
TCE input setup/hold with respect to CLK. 0.34/0.01 0.51/0.01 0.51/0.01 ns
Sequential Delays
T
OSCKO_OQ
Clock to out from CLK to OQ. 0.42 0.48 0.48 ns
T
OSCKO_TQ
Clock to out from CLK to TQ. 0.49 0.56 0.56 ns
Combinatorial
T
OSDO_TTQ
T input to TQ out. 0.92 1.11 1.11 ns
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