Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 26
Input Serializer/Deserializer Switching Characteristics
Table 23: ISERDES Switching Characteristics
Symbol Description
V
CCINT
Operating Voltage and Speed
Grade
Units
1.0V 0.95V
-2 -1 -1L
Setup/Hold for Control Lines
T
ISCCK_BITSLIP
/
T
ISCKC_BITSLIP
BITSLIP pin setup/hold with respect to
CLKDIV.
0.02/0.15 0.02/0.17 0.02/0.17 ns
T
ISCCK_CE
/
T
ISCKC_CE
CE pin setup/hold with respect to CLK
(for CE1).
0.50/–0.01 0.72/–0.01 0.72/–0.01 ns
T
ISCCK_CE2
/
T
ISCKC_CE2
CE pin setup/hold with respect to CLKDIV
(for CE2).
–0.10/0.36 –0.10/0.40 –0.10/0.40 ns
Setup/Hold for Data Lines
T
ISDCK_D
/
T
ISCKD_D
D pin setup/hold with respect to CLK. –0.02/0.14 –0.02/0.17 –0.02/0.17 ns
T
ISDCK_DDLY
/
T
ISCKD_DDLY
DDLY pin setup/hold with respect to CLK
(using IDELAY).
(1)
–0.02/0.14 –0.02/0.17 –0.02/0.17 ns
T
ISDCK_D_DDR
/
T
ISCKD_D_DDR
D pin setup/hold with respect to CLK at
DDR mode.
–0.02/0.14 –0.02/0.17 –0.02/0.17 ns
T
ISDCK_DDLY_DDR
/
T
ISCKD_DDLY_DDR
D pin setup/hold with respect to CLK at
DDR mode (using IDELAY).
(1)
0.14/0.14 0.17/0.17 0.17/0.17 ns
Sequential Delays
T
ISCKO_Q
CLKDIV to out at Q pin. 0.54 0.66 0.66 ns
Propagation Delays
T
ISDO_DO
D input to DO output pin. 0.11 0.13 0.13 ns
Notes:
1. Recorded at 0 tap value.
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