Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 20
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 19 shows the test setup parameters used for measuring input delay.
Table 19: Input Delay Measurement Methodology
Description I/O Standard Attribute V
L
(1)
V
H
(1)
V
MEAS
(3)(5)
V
REF
(2)(4)
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 –
LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 –
LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 –
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 –
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 –
LVTTL, 3.3V LVTTL 0.1 3.2 1.65 –
MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 –
PCI33, 3.3V PCI33_3 0.1 3.2 1.65 –
HSTL (high-speed transceiver
logic), Class I, 1.2V
HSTL_I_12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
HSTL, Class I & II, 1.5V HSTL_I, HSTL_II V
REF
–0.65 V
REF
+0.65 V
REF
0.75
HSTL, Class I & II, 1.8V
HSTL_I_18,
HSTL_II_18
V
REF
–0.8 V
REF
+0.8 V
REF
0.90
HSUL (high-speed
unterminated logic), 1.2V
HSUL_12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
SSTL (stub-terminated
transceiver logic), 1.2V
SSTL12 V
REF
–0.5 V
REF
+0.5 V
REF
0.60
SSTL, 1.35V SSTL135, SSTL135_R V
REF
–0.575 V
REF
+0.575 V
REF
0.675
SSTL, 1.5V SSTL15, SSTL15_R V
REF
–0.65 V
REF
+0.65 V
REF
0.75
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V
REF
–0.8 V
REF
+0.8 V
REF
0.90
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0
(5)
–
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0
(5)
–
DIFF_HSTL, Class I & II,1.5V
DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0
(5)
–
DIFF_HSTL, Class I & II, 1.8V
DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0
(5)
–
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0
(5)
–
DIFF_SSTL135/
DIFF_SSTL135_R, 1.35V
DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125 0
(5)
–
DIFF_SSTL15/
DIFF_SSTL15_R, 1.5V
DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0
(5)
–
DIFF_SSTL18_I/
DIFF_SSTL18_II, 1.8V
DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0
(5)
–
LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0
(5)
–
BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0
(5)
–
MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0
(5)
–
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