Datasheet
Table Of Contents
- Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
- Introduction
- DC Characteristics
- Power-On/Off Power Supply Sequencing
- DC Input and Output Levels
- AC Switching Characteristics
- Performance Characteristics
- IOB Pad Input/Output/3-State
- I/O Standard Adjustment Measurement Methodology
- Input/Output Logic Switching Characteristics
- Input Serializer/Deserializer Switching Characteristics
- Output Serializer/Deserializer Switching Characteristics
- Input/Output Delay Switching Characteristics
- CLB Switching Characteristics
- CLB Distributed RAM Switching Characteristics (SLICEM Only)
- CLB Shift Register Switching Characteristics (SLICEM Only)
- Block RAM and FIFO Switching Characteristics
- DSP48E1 Switching Characteristics
- Clock Buffers and Networks
- MMCM Switching Characteristics
- PLL Switching Characteristics
- Device Pin-to-Pin Output Parameter Guidelines
- Device Pin-to-Pin Input Parameter Guidelines
- Additional Package Parameter Guidelines
- XADC Specifications
- Configuration Switching Characteristics
- eFUSE Programming Conditions
- References
- Revision History
- Please Read: Important Legal Notices
Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS189 (v1.9) March 13, 2019 www.xilinx.com
Product Specification 18
Table 18 specifies the values of T
IOTPHZ
and T
IOIBUFDISABLE
. T
IOTPHZ
is described as the delay from the T pin
to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance
state). T
IOIBUFDISABLE
is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the
internal IN_TERM termination turn-off time is always faster than T
IOTPHZ
when the INTERMDISABLE pin is
used.
LVCMOS15_F8 0.860.930.931.721.981.981.751.991.99ns
LVCMOS15_F12 0.86 0.93 0.93 1.47 1.73 1.73 1.50 1.74 1.74 ns
LVCMOS15_F16 0.86 0.93 0.93 1.46 1.71 1.71 1.49 1.73 1.73 ns
LVCMOS12_S4 0.951.021.022.692.952.952.722.962.96ns
LVCMOS12_S8 0.951.021.022.212.462.462.242.482.48ns
LVCMOS12_S12 0.95 1.02 1.02 1.91 2.17 2.17 1.94 2.18 2.18 ns
LVCMOS12_F4 0.951.021.022.102.352.352.132.372.37ns
LVCMOS12_F8 0.951.021.021.661.921.921.691.931.93ns
LVCMOS12_F12 0.95 1.02 1.02 1.51 1.76 1.76 1.54 1.77 1.77 ns
SSTL135_S 0.75 0.82 0.82 1.47 1.73 1.73 1.50 1.74 1.74 ns
SSTL15_S 0.68 0.75 0.75 1.43 1.68 1.68 1.46 1.69 1.69 ns
SSTL18_I_S 0.75 0.82 0.82 1.79 2.04 2.04 1.82 2.06 2.06 ns
SSTL18_II_S 0.750.820.821.431.681.681.461.701.70ns
DIFF_SSTL135_S 0.76 0.83 0.83 1.47 1.73 1.73 1.50 1.74 1.74 ns
DIFF_SSTL15_S 0.76 0.83 0.83 1.43 1.68 1.68 1.46 1.69 1.69 ns
DIFF_SSTL18_I_S 0.79 0.86 0.86 1.80 2.06 2.06 1.83 2.07 2.07 ns
DIFF_SSTL18_II_S 0.790.860.861.511.761.761.541.771.77ns
SSTL135_F 0.75 0.82 0.82 1.24 1.49 1.49 1.27 1.51 1.51 ns
SSTL15_F 0.68 0.75 0.75 1.19 1.45 1.45 1.22 1.46 1.46 ns
SSTL18_I_F 0.75 0.82 0.82 1.24 1.49 1.49 1.27 1.51 1.51 ns
SSTL18_II_F 0.750.820.821.241.491.491.271.511.51ns
DIFF_SSTL135_F 0.76 0.83 0.83 1.24 1.49 1.49 1.27 1.51 1.51 ns
DIFF_SSTL15_F 0.76 0.83 0.83 1.19 1.45 1.45 1.22 1.46 1.46 ns
DIFF_SSTL18_I_F 0.79 0.86 0.86 1.35 1.60 1.60 1.38 1.62 1.62 ns
DIFF_SSTL18_II_F 0.790.860.861.331.591.591.361.601.60ns
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
T
IOPI
T
IOOP
T
IOTP
Units
V
CCINT
Operating Voltage and Speed Grade
1.0V 0.95V 1.0V 0.95V 1.0V 0.95V
-2 -1 -1L -2 -1 -1L -2 -1 -1L
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